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| Started by | Romain Perier <romain.perier@collabora.com> |
|---|---|
| First post | 2017-06-30 15:50 +0200 |
| Last post | 2017-07-02 15:50 +0200 |
| Articles | 2 — 2 participants |
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[PATCH] ARM: dts: imx: Correct B850v3 clock assignment Romain Perier <romain.perier@collabora.com> - 2017-06-30 15:50 +0200
Re: [PATCH] ARM: dts: imx: Correct B850v3 clock assignment Fabio Estevam <festevam@gmail.com> - 2017-07-02 15:50 +0200
| From | Romain Perier <romain.perier@collabora.com> |
|---|---|
| Date | 2017-06-30 15:50 +0200 |
| Subject | [PATCH] ARM: dts: imx: Correct B850v3 clock assignment |
| Message-ID | <tY4t5-682-27@gated-at.bofh.it> |
From: Martyn Welch <martyn.welch@collabora.co.uk> The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m to avoid stepping on the LVDS output's toes, as the PLL can't be clocked to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the same time. As we are using ipu1_di0 and ipu2_di0, ensure both are switched to to pll2_pfd2_396m to avoid issues. The LDB driver will switch the required IPU to ldb_di1 when it uses it to drive LVDS. Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> --- arch/arm/boot/dts/imx6q-b850v3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 2c1e98e..46bdc67 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -57,7 +57,7 @@ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, -- 1.8.3.1
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| From | Fabio Estevam <festevam@gmail.com> |
|---|---|
| Date | 2017-07-02 15:50 +0200 |
| Message-ID | <tYNq9-2Fy-5@gated-at.bofh.it> |
| In reply to | #1678844 |
On Fri, Jun 30, 2017 at 10:43 AM, Romain Perier <romain.perier@collabora.com> wrote: > From: Martyn Welch <martyn.welch@collabora.co.uk> > > The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m > to avoid stepping on the LVDS output's toes, as the PLL can't be clocked > to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the > same time. > > As we are using ipu1_di0 and ipu2_di0, ensure both are switched to > to pll2_pfd2_396m to avoid issues. The LDB driver will switch the > required IPU to ldb_di1 when it uses it to drive LVDS. > > Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> > Signed-off-by: Romain Perier <romain.perier@collabora.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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