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[PATCH 4/8] arm64: dts: allwinner: a64: add SCPI support

Started byAndre Przywara <andre.przywara@arm.com>
First post2017-06-30 12:10 +0200
Last post2017-06-30 12:10 +0200
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  [PATCH 4/8] arm64: dts: allwinner: a64: add SCPI support Andre Przywara <andre.przywara@arm.com> - 2017-06-30 12:10 +0200

#1678650 — [PATCH 4/8] arm64: dts: allwinner: a64: add SCPI support

FromAndre Przywara <andre.przywara@arm.com>
Date2017-06-30 12:10 +0200
Subject[PATCH 4/8] arm64: dts: allwinner: a64: add SCPI support
Message-ID<tY12a-497-23@gated-at.bofh.it>
This adds support for the SCPI protocol using an SMC mailbox and some
shared memory in SRAM.
The SCPI provider is implemented in the ARM Trusted Firmware layer
(running in EL3 on the application processor cores), triggered by an smc
call.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 9d00622..ef6f10e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -124,6 +124,32 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	mailbox: mbox@0 {
+		compatible = "arm,smc-mbox";
+		#mbox-cells = <1>;
+		arm,smc-func-ids = <0x82000001>;
+	};
+
+	sram: sram@10000{
+		compatible = "mmio-sram";
+		reg = <0x10000 0x8000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x10000 0x8000>;
+
+		cpu_scp_mem: scp-shmem@7e00 {
+			compatible = "mmio-sram";
+			reg = <0x7e00 0x200>;
+		};
+	};
+
+	scpi {
+		compatible = "arm,scpi";
+		mboxes = <&mailbox 0>;
+		shmem = <&cpu_scp_mem>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
2.9.0

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