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Groups > linux.kernel > #1676888 > unrolled thread
| Started by | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| First post | 2017-06-28 18:10 +0200 |
| Last post | 2017-06-28 18:10 +0200 |
| Articles | 9 — 3 participants |
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[PATCH v2 00/10] MIPS: Add virtual Ranchu board as a generic-based board Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
[PATCH v2 07/10] video: goldfishfb: Add support for device tree bindings Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
[PATCH v2 09/10] MIPS: i8042: Probe this device only if it exists Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
[PATCH v2 06/10] Documentation: Add device tree binding for Goldfish FB driver Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
Re: [PATCH v2 06/10] Documentation: Add device tree binding for Goldfish FB driver Rob Herring <robh+dt@kernel.org> - 2017-06-30 01:20 +0200
[PATCH v2 04/10] MIPS: ranchu: Add Goldfish PIC driver Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
Re: [PATCH v2 04/10] MIPS: ranchu: Add Goldfish PIC driver Marc Zyngier <marc.zyngier@arm.com> - 2017-06-28 20:00 +0200
[PATCH v2 02/10] MIPS: ranchu: Add Goldfish RTC driver Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
[PATCH v2 01/10] Documentation: Add device tree binding for Goldfish RTC driver Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-06-28 18:10 +0200
| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 00/10] MIPS: Add virtual Ranchu board as a generic-based board |
| Message-ID | <tXnxM-hR-23@gated-at.bofh.it> |
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
v1->v2:
- patch on RTC driver cleaned up
- added drivers for virtio console and net to the Ranchu board
- minor improvements in commit messages
- updated recipient lists using get_maintainer.pl
- rebased to the latest code
This series adds Mips Ranchu virtual machine used by Android emulator.
The board relies on the concept of Mips generic boards, and utilizes
generic board framework for build and device organization.
The Ranchu board is intended to be used by Android emulator.The name
"Ranchu" originates from Android development community. "Goldfish" and
"Ranchu" are names for two generations of virtual boards used by
Android emulator. "Ranchu" is a newer one among the two, and this
series deals with Ranchu. However, for historical reasons, some file,
device, and variable names in this series still contain the word
"Goldfish".
Mips Ranchu machine includes a number of Goldfish devices. The
support for Virtio devices is also included. Ranchu board supports
up to 16 virtio devices which can be attached using virtio MMIO Bus.
This is summarized in the following picture:
ABUS
||----MIPS CPU
|| | IRQs
||----Goldfish PIC------------(32)--------
|| | | | | | | | | |
||----Goldfish TTY------ | | | | | | | |
|| | | | | | | | |
||----Goldfish RTC-------- | | | | | | |
|| | | | | | | |
||----Goldfish FB----------- | | | | | |
|| | | | | | |
||----Goldfish Events--------- | | | | |
|| | | | | |
||----Goldfish Audio------------ | | | |
|| | | | |
||----Goldfish Battery------------ | | |
|| | | |
||----Android PIPE------------------ | |
|| | |
||----Virtio MMIO Bus | |
|| | | | | |
|| | | (virtio-block)--------- |
|| (16) | |
|| | (virtio-net)------------------
Device Tree is created on the QEMU side based on the information about
devices IO map and IRQ numbers. Kernel will load this DTB using UHI
boot protocol.
Checkpatch script outputs a small number of warnings if applied to
this series. We did not correct the code, since we think the code is
correct for those particular cases of checkpatch warnings.
Aleksandar Markovic (6):
Documentation: Add device tree binding for Goldfish RTC driver
MIPS: ranchu: Add Goldfish RTC driver
Documentation: Add device tree binding for Goldfish PIC driver
MIPS: ranchu: Add Goldfish PIC driver
Documentation: Add device tree binding for Goldfish FB driver
video: goldfishfb: Add support for device tree bindings
Miodrag Dinic (4):
MIPS: ranchu: Add Ranchu as a new generic-based board
MIPS: Introduce check_legacy_ioport() interface
MIPS: i8042: Probe this device only if it exists
MIPS: generic: Add optional support for Android kernel
.../bindings/goldfish/google,goldfish-fb.txt | 18 +++
.../interrupt-controller/google,goldfish-pic.txt | 18 +++
.../bindings/rtc/google,goldfish-rtc.txt | 17 ++
MAINTAINERS | 19 +++
arch/mips/Makefile | 8 +-
arch/mips/configs/generic/android.config | 173 +++++++++++++++++++++
arch/mips/configs/generic/board-ranchu.config | 25 +++
arch/mips/generic/Kconfig | 11 ++
arch/mips/generic/Makefile | 1 +
arch/mips/generic/board-ranchu.c | 83 ++++++++++
arch/mips/include/asm/io.h | 5 +
arch/mips/kernel/setup.c | 41 +++++
drivers/input/serio/i8042-io.h | 2 +-
drivers/irqchip/Kconfig | 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-goldfish-pic.c | 169 ++++++++++++++++++++
drivers/rtc/Kconfig | 6 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-goldfish.c | 136 ++++++++++++++++
drivers/video/fbdev/goldfishfb.c | 8 +-
20 files changed, 747 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/goldfish/google,goldfish-fb.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
create mode 100644 Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
create mode 100644 arch/mips/configs/generic/android.config
create mode 100644 arch/mips/configs/generic/board-ranchu.config
create mode 100644 arch/mips/generic/board-ranchu.c
create mode 100644 drivers/irqchip/irq-goldfish-pic.c
create mode 100644 drivers/rtc/rtc-goldfish.c
--
2.7.4
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| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 07/10] video: goldfishfb: Add support for device tree bindings |
| Message-ID | <tXnHr-AC-15@gated-at.bofh.it> |
| In reply to | #1676888 |
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Add ability to the Goldfish FB driver to be recognized by OS via DT.
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
drivers/video/fbdev/goldfishfb.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/video/fbdev/goldfishfb.c b/drivers/video/fbdev/goldfishfb.c
index 7f6c9e6..3b70044 100644
--- a/drivers/video/fbdev/goldfishfb.c
+++ b/drivers/video/fbdev/goldfishfb.c
@@ -304,12 +304,18 @@ static int goldfish_fb_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id goldfish_fb_of_match[] = {
+ { .compatible = "google,goldfish-fb", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, goldfish_fb_of_match);
static struct platform_driver goldfish_fb_driver = {
.probe = goldfish_fb_probe,
.remove = goldfish_fb_remove,
.driver = {
- .name = "goldfish_fb"
+ .name = "goldfish_fb",
+ .of_match_table = goldfish_fb_of_match,
}
};
--
2.7.4
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| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 09/10] MIPS: i8042: Probe this device only if it exists |
| Message-ID | <tXnHs-AC-17@gated-at.bofh.it> |
| In reply to | #1676888 |
From: Miodrag Dinic <miodrag.dinic@imgtec.com>
ARCH_MIGHT_HAVE_PC_SERIO is selected by default for MIPS platforms.
As a consequence SERIO_I8042 would be automatically selected for any
MIPS board which wants to enable input support like keyboard
(INPUT_KEYBOARD) regardless of i8042 controller existence.
The dependency is as follows :
config ARCH_MIGHT_HAVE_PC_SERIO [=y]
Defined at drivers/input/serio/Kconfig:19
Depends on: !UML
Selected by: MIPS [=y]
config SERIO
Defined at drivers/input/serio/Kconfig:4
default y
Depends on: !UML
Selected by: KEYBOARD_ATKBD [=y] && !UML && INPUT [=y] &&
INPUT_KEYBOARD [=y]
config SERIO_I8042
Defined at drivers/input/serio/Kconfig:28
tristate "i8042 PC Keyboard controller"
default y
Depends on: !UML && SERIO [=y] && ARCH_MIGHT_HAVE_PC_SERIO [=y]
Selected by: KEYBOARD_ATKBD [=y] && !UML && INPUT [=y] &&
INPUT_KEYBOARD [=y] && ARCH_MIGHT_HAVE_PC_SERIO [=y]
If this driver probes the I8042_DATA_REG not knowing if the device
exists it can cause a kernel to crash. Using check_legacy_ioport()
interface we can selectively enable this driver only for the MIPS
boards which actually have the i8042 controller.
New "Ranchu" virtual platform does not support i8042 controller
so it's added to the blacklist match table.
Each MIPS machine should update this table with it's compatible strings
if it does not support i8042 controller.
In order to utilize this mechanism, each MIPS machine that do not
have i8042 controller should update the blacklist table with its
compatible strings.
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
arch/mips/kernel/setup.c | 16 ++++++++++++++++
drivers/input/serio/i8042-io.h | 2 +-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index c22cde8..c3e0d2b 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -79,6 +79,15 @@ const unsigned long mips_io_port_base = -1;
EXPORT_SYMBOL(mips_io_port_base);
/*
+ * Here we blacklist all MIPS boards which do not have i8042 controller
+ */
+static const struct of_device_id i8042_blacklist_of_match[] = {
+ { .compatible = "mti,ranchu", },
+ {},
+};
+#define I8042_DATA_REG 0x60
+
+/*
* Check for existence of legacy devices
*
* Some drivers may try to probe some I/O ports which can lead to
@@ -90,9 +99,16 @@ EXPORT_SYMBOL(mips_io_port_base);
*/
int check_legacy_ioport(unsigned long base_port)
{
+ struct device_node *np;
int ret = 0;
switch (base_port) {
+ case I8042_DATA_REG:
+ np = of_find_matching_node(NULL, i8042_blacklist_of_match);
+ if (np)
+ ret = -ENODEV;
+ of_node_put(np);
+ break;
default:
/* We will assume that the I/O device port exists if
* not explicitly added to the blacklist match table
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 34da81c..ec5fe9e 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -72,7 +72,7 @@ static inline int i8042_platform_init(void)
* On some platforms touching the i8042 data register region can do really
* bad things. Because of this the region is always reserved on such boxes.
*/
-#if defined(CONFIG_PPC)
+#if defined(CONFIG_PPC) || defined(CONFIG_MIPS)
if (check_legacy_ioport(I8042_DATA_REG))
return -ENODEV;
#endif
--
2.7.4
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| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 06/10] Documentation: Add device tree binding for Goldfish FB driver |
| Message-ID | <tXnHs-AC-23@gated-at.bofh.it> |
| In reply to | #1676888 |
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Add documentation for DT binding of Goldfish FB driver. The compatible
string used by OS for binding the driver is "google,goldfish-fb".
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
.../bindings/goldfish/google,goldfish-fb.txt | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
create mode 100644 Documentation/devicetree/bindings/goldfish/google,goldfish-fb.txt
diff --git a/Documentation/devicetree/bindings/goldfish/google,goldfish-fb.txt b/Documentation/devicetree/bindings/goldfish/google,goldfish-fb.txt
new file mode 100644
index 0000000..9ce0615
--- /dev/null
+++ b/Documentation/devicetree/bindings/goldfish/google,goldfish-fb.txt
@@ -0,0 +1,18 @@
+Android Goldfish framebuffer
+
+Android Goldfish framebuffer device used by Android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-fb"
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish_fb@1f008000 {
+ compatible = "google,goldfish-fb";
+ interrupts = <0x10>;
+ reg = <0x1f008000 0x0 0x100>;
+ compatible = "google,goldfish-fb";
+ };
--
2.7.4
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| From | Rob Herring <robh+dt@kernel.org> |
|---|---|
| Date | 2017-06-30 01:20 +0200 |
| Subject | Re: [PATCH v2 06/10] Documentation: Add device tree binding for Goldfish FB driver |
| Message-ID | <tXQT9-5RT-23@gated-at.bofh.it> |
| In reply to | #1676894 |
On Wed, Jun 28, 2017 at 10:46 AM, Aleksandar Markovic <aleksandar.markovic@rt-rk.com> wrote: > From: Aleksandar Markovic <aleksandar.markovic@imgtec.com> > > Add documentation for DT binding of Goldfish FB driver. The compatible > string used by OS for binding the driver is "google,goldfish-fb". > > Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> > Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> > Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> > --- > .../bindings/goldfish/google,goldfish-fb.txt | 18 ++++++++++++++++++ bindings/display/ I don't know that this should even go upstream. There's no upstream qemu support for goldfish-fb. Maybe this is a minor driver change, but FB drivers are being replaced with DRM drivers. And the time for AOSP supporting framebuffer drivers is limited I think with HWC2 and explicit fence support in DRM. Rob
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| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 04/10] MIPS: ranchu: Add Goldfish PIC driver |
| Message-ID | <tXnHs-AC-27@gated-at.bofh.it> |
| In reply to | #1676888 |
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Add device driver for a virtual programmable interrupt controller
The virtual PIC is designed as a device tree-based interrupt controller.
The compatible string used by OS for binding the driver is
"google,goldfish-pic".
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
MAINTAINERS | 1 +
drivers/irqchip/Kconfig | 9 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-goldfish-pic.c | 169 +++++++++++++++++++++++++++++++++++++
4 files changed, 180 insertions(+)
create mode 100644 drivers/irqchip/irq-goldfish-pic.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 85da9f0..fb4c6ea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -845,6 +845,7 @@ ANDROID GOLDFISH PIC DRIVER
M: Miodrag Dinic <miodrag.dinic@imgtec.com>
S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
+F: drivers/irqchip/irq-goldfish-pic.c
ANDROID GOLDFISH RTC DRIVER
M: Miodrag Dinic <miodrag.dinic@imgtec.com>
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 478f8ac..6c2f924 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -301,3 +301,12 @@ config QCOM_IRQ_COMBINER
help
Say yes here to add support for the IRQ combiner devices embedded
in Qualcomm Technologies chips.
+
+config GOLDFISH_PIC
+ bool "Goldfish programmable interrupt controller"
+ depends on MIPS
+ depends on GOLDFISH
+ select IRQ_DOMAIN
+ help
+ Say yes here to enable Goldfish interrupt controller driver used
+ for Goldfish based virtual platforms.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b64c59b..5e73932 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
+obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldfish-pic.c
new file mode 100644
index 0000000..d0e4c2d
--- /dev/null
+++ b/drivers/irqchip/irq-goldfish-pic.c
@@ -0,0 +1,169 @@
+/* drivers/irqchip/irq-goldfish-pic.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (C) 2017 Imagination Technologies Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/setup.h>
+
+/* 0..7 MIPS CPU interrupts */
+#define GOLDFISH_CPU_IRQ_PIC (MIPS_CPU_IRQ_BASE + 2)
+#define GOLDFISH_CPU_IRQ_FIQ (MIPS_CPU_IRQ_BASE + 3) /* Not used? */
+#define GOLDFISH_CPU_IRQ_COMPARE (MIPS_CPU_IRQ_BASE + 7)
+
+#define GOLDFISH_NR_IRQS 40
+/* 8..39 Cascaded Goldfish PIC interrupts */
+#define GOLDFISH_IRQ_OFFSET 8
+
+#define GOLDFISH_PIC_NUMBER 0x04
+#define GOLDFISH_PIC_DISABLE_ALL 0x08
+#define GOLDFISH_PIC_DISABLE 0x0c
+#define GOLDFISH_PIC_ENABLE 0x10
+
+static struct irq_domain *goldfish_pic_domain;
+static void __iomem *goldfish_pic_base;
+
+void goldfish_mask_irq(struct irq_data *d)
+{
+ writel(d->irq - GOLDFISH_IRQ_OFFSET,
+ goldfish_pic_base + GOLDFISH_PIC_DISABLE);
+}
+
+void goldfish_unmask_irq(struct irq_data *d)
+{
+ writel(d->irq - GOLDFISH_IRQ_OFFSET,
+ goldfish_pic_base + GOLDFISH_PIC_ENABLE);
+}
+
+static struct irq_chip goldfish_irq_chip = {
+ .name = "goldfish",
+ .irq_mask = goldfish_mask_irq,
+ .irq_mask_ack = goldfish_mask_irq,
+ .irq_unmask = goldfish_unmask_irq,
+};
+
+void goldfish_irq_dispatch(void)
+{
+ uint32_t irq;
+
+ /*
+ * Disable all interrupt sources
+ */
+ irq = readl(goldfish_pic_base + GOLDFISH_PIC_NUMBER);
+ do_IRQ(GOLDFISH_IRQ_OFFSET + irq);
+}
+
+void goldfish_fiq_dispatch(void)
+{
+ panic("goldfish_fiq_dispatch");
+}
+
+static void goldfish_ip2_irq_dispatch(struct irq_desc *desc)
+{
+ unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+ if (pending & CAUSEF_IP2)
+ goldfish_irq_dispatch();
+ else if (pending & CAUSEF_IP3)
+ goldfish_fiq_dispatch();
+ else if (pending & CAUSEF_IP7)
+ do_IRQ(MIPS_CPU_IRQ_BASE + 7);
+ else
+ spurious_interrupt();
+}
+
+static struct irqaction cascade = {
+ .handler = no_action,
+ .flags = IRQF_NO_THREAD,
+ .name = "cascade",
+};
+
+static void mips_timer_dispatch(void)
+{
+ do_IRQ(MIPS_CPU_IRQ_BASE + GOLDFISH_CPU_IRQ_COMPARE);
+}
+
+static int goldfish_pic_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hw)
+{
+ struct irq_chip *chip = &goldfish_irq_chip;
+
+ if (hw < GOLDFISH_IRQ_OFFSET)
+ return 0;
+
+ irq_set_chip_and_handler(hw, chip, handle_level_irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+ .xlate = irq_domain_xlate_onetwocell,
+ .map = goldfish_pic_map,
+};
+
+int __init goldfish_pic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct resource res;
+
+ if (of_address_to_resource(node, 0, &res)) {
+ pr_err("%s(): Failed to get icu memory range", __func__);
+ return -ENODEV;
+ }
+
+ if (request_mem_region(res.start, resource_size(&res),
+ res.name) < 0) {
+ pr_err("%s(): Failed to request icu memory", __func__);
+ return -ENOMEM;
+ }
+
+ goldfish_pic_base = ioremap_nocache(res.start, resource_size(&res));
+ if (!goldfish_pic_base) {
+ pr_err("%s(): Failed to remap icu memory", __func__);
+ release_mem_region(res.start, resource_size(&res));
+ return -ENOMEM;
+ }
+
+ /*
+ * Disable all interrupt sources
+ */
+ writel(1, goldfish_pic_base + GOLDFISH_PIC_DISABLE_ALL);
+
+ if (cpu_has_vint) {
+ pr_info("Setting up vectored interrupts\n");
+ set_vi_handler(GOLDFISH_CPU_IRQ_PIC, goldfish_irq_dispatch);
+ set_vi_handler(GOLDFISH_CPU_IRQ_FIQ, goldfish_fiq_dispatch);
+ set_vi_handler(GOLDFISH_CPU_IRQ_COMPARE, mips_timer_dispatch);
+ } else {
+ irq_set_chained_handler(GOLDFISH_CPU_IRQ_PIC,
+ goldfish_ip2_irq_dispatch);
+ }
+
+ setup_irq(MIPS_CPU_IRQ_BASE+GOLDFISH_CPU_IRQ_PIC, &cascade);
+ setup_irq(MIPS_CPU_IRQ_BASE+GOLDFISH_CPU_IRQ_FIQ, &cascade);
+
+ goldfish_pic_domain = irq_domain_add_linear(node, GOLDFISH_NR_IRQS,
+ &irq_domain_ops, 0);
+ if (!goldfish_pic_domain)
+ panic("Failed to add IRQ domain");
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(google_goldfish_pic, "google,goldfish-pic",
+ goldfish_pic_of_init);
--
2.7.4
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| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Date | 2017-06-28 20:00 +0200 |
| Subject | Re: [PATCH v2 04/10] MIPS: ranchu: Add Goldfish PIC driver |
| Message-ID | <tXpq0-t5-123@gated-at.bofh.it> |
| In reply to | #1676895 |
On 28/06/17 16:46, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
>
> Add device driver for a virtual programmable interrupt controller
>
> The virtual PIC is designed as a device tree-based interrupt controller.
>
> The compatible string used by OS for binding the driver is
> "google,goldfish-pic".
>
> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
> MAINTAINERS | 1 +
> drivers/irqchip/Kconfig | 9 ++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-goldfish-pic.c | 169 +++++++++++++++++++++++++++++++++++++
> 4 files changed, 180 insertions(+)
> create mode 100644 drivers/irqchip/irq-goldfish-pic.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 85da9f0..fb4c6ea 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -845,6 +845,7 @@ ANDROID GOLDFISH PIC DRIVER
> M: Miodrag Dinic <miodrag.dinic@imgtec.com>
> S: Supported
> F: Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
> +F: drivers/irqchip/irq-goldfish-pic.c
>
> ANDROID GOLDFISH RTC DRIVER
> M: Miodrag Dinic <miodrag.dinic@imgtec.com>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 478f8ac..6c2f924 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -301,3 +301,12 @@ config QCOM_IRQ_COMBINER
> help
> Say yes here to add support for the IRQ combiner devices embedded
> in Qualcomm Technologies chips.
> +
> +config GOLDFISH_PIC
> + bool "Goldfish programmable interrupt controller"
> + depends on MIPS
> + depends on GOLDFISH
> + select IRQ_DOMAIN
> + help
> + Say yes here to enable Goldfish interrupt controller driver used
> + for Goldfish based virtual platforms.
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b64c59b..5e73932 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -76,3 +76,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
> obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
> obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
> +obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
> diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldfish-pic.c
> new file mode 100644
> index 0000000..d0e4c2d
> --- /dev/null
> +++ b/drivers/irqchip/irq-goldfish-pic.c
> @@ -0,0 +1,169 @@
> +/* drivers/irqchip/irq-goldfish-pic.c
> + *
> + * Copyright (C) 2007 Google, Inc.
> + * Copyright (C) 2017 Imagination Technologies Ltd.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irqchip.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include <asm/setup.h>
> +
> +/* 0..7 MIPS CPU interrupts */
> +#define GOLDFISH_CPU_IRQ_PIC (MIPS_CPU_IRQ_BASE + 2)
> +#define GOLDFISH_CPU_IRQ_FIQ (MIPS_CPU_IRQ_BASE + 3) /* Not used? */
> +#define GOLDFISH_CPU_IRQ_COMPARE (MIPS_CPU_IRQ_BASE + 7)
> +
> +#define GOLDFISH_NR_IRQS 40
> +/* 8..39 Cascaded Goldfish PIC interrupts */
> +#define GOLDFISH_IRQ_OFFSET 8
> +
> +#define GOLDFISH_PIC_NUMBER 0x04
> +#define GOLDFISH_PIC_DISABLE_ALL 0x08
> +#define GOLDFISH_PIC_DISABLE 0x0c
> +#define GOLDFISH_PIC_ENABLE 0x10
> +
> +static struct irq_domain *goldfish_pic_domain;
> +static void __iomem *goldfish_pic_base;
> +
> +void goldfish_mask_irq(struct irq_data *d)
> +{
> + writel(d->irq - GOLDFISH_IRQ_OFFSET,
> + goldfish_pic_base + GOLDFISH_PIC_DISABLE);
This makes exactly zero sense. You're using the Linux irq, which is just
a random number, and write that to the HW?
> +}
> +
> +void goldfish_unmask_irq(struct irq_data *d)
> +{
> + writel(d->irq - GOLDFISH_IRQ_OFFSET,
> + goldfish_pic_base + GOLDFISH_PIC_ENABLE);
> +}
> +
> +static struct irq_chip goldfish_irq_chip = {
> + .name = "goldfish",
> + .irq_mask = goldfish_mask_irq,
> + .irq_mask_ack = goldfish_mask_irq,
> + .irq_unmask = goldfish_unmask_irq,
> +};
> +
> +void goldfish_irq_dispatch(void)
> +{
> + uint32_t irq;
> +
> + /*
> + * Disable all interrupt sources
> + */
> + irq = readl(goldfish_pic_base + GOLDFISH_PIC_NUMBER);
> + do_IRQ(GOLDFISH_IRQ_OFFSET + irq);
> +}
> +
> +void goldfish_fiq_dispatch(void)
> +{
> + panic("goldfish_fiq_dispatch");
> +}
> +
> +static void goldfish_ip2_irq_dispatch(struct irq_desc *desc)
> +{
> + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
> +
> + if (pending & CAUSEF_IP2)
> + goldfish_irq_dispatch();
> + else if (pending & CAUSEF_IP3)
> + goldfish_fiq_dispatch();
> + else if (pending & CAUSEF_IP7)
> + do_IRQ(MIPS_CPU_IRQ_BASE + 7);
> + else
> + spurious_interrupt();
> +}
> +
> +static struct irqaction cascade = {
> + .handler = no_action,
> + .flags = IRQF_NO_THREAD,
> + .name = "cascade",
> +};
> +
> +static void mips_timer_dispatch(void)
> +{
> + do_IRQ(MIPS_CPU_IRQ_BASE + GOLDFISH_CPU_IRQ_COMPARE);
> +}
> +
> +static int goldfish_pic_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hw)
> +{
> + struct irq_chip *chip = &goldfish_irq_chip;
> +
> + if (hw < GOLDFISH_IRQ_OFFSET)
> + return 0;
> +
> + irq_set_chip_and_handler(hw, chip, handle_level_irq);
Ah, right. No. Really. You're completely confusing irq and hwirq. You
really have to chose: either your system is DT driven, and you
completely disassociate irq and hwirq (that's what the irq domain is
for), or it is the same thing, and there is no irq domain (and no DT
either).
As it stands, this looks like a driver that has been DT-ified in a
hurry, without actually trying to make it fit in.
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops irq_domain_ops = {
> + .xlate = irq_domain_xlate_onetwocell,
> + .map = goldfish_pic_map,
> +};
> +
> +int __init goldfish_pic_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct resource res;
> +
> + if (of_address_to_resource(node, 0, &res)) {
> + pr_err("%s(): Failed to get icu memory range", __func__);
> + return -ENODEV;
> + }
> +
> + if (request_mem_region(res.start, resource_size(&res),
> + res.name) < 0) {
> + pr_err("%s(): Failed to request icu memory", __func__);
> + return -ENOMEM;
> + }
> +
> + goldfish_pic_base = ioremap_nocache(res.start, resource_size(&res));
All of the above should replaced by a single of_iomap.
> + if (!goldfish_pic_base) {
> + pr_err("%s(): Failed to remap icu memory", __func__);
> + release_mem_region(res.start, resource_size(&res));
> + return -ENOMEM;
> + }
> +
> + /*
> + * Disable all interrupt sources
> + */
> + writel(1, goldfish_pic_base + GOLDFISH_PIC_DISABLE_ALL);
> +
> + if (cpu_has_vint) {
> + pr_info("Setting up vectored interrupts\n");
> + set_vi_handler(GOLDFISH_CPU_IRQ_PIC, goldfish_irq_dispatch);
> + set_vi_handler(GOLDFISH_CPU_IRQ_FIQ, goldfish_fiq_dispatch);
> + set_vi_handler(GOLDFISH_CPU_IRQ_COMPARE, mips_timer_dispatch);
> + } else {
> + irq_set_chained_handler(GOLDFISH_CPU_IRQ_PIC,
> + goldfish_ip2_irq_dispatch);
> + }
> +
> + setup_irq(MIPS_CPU_IRQ_BASE+GOLDFISH_CPU_IRQ_PIC, &cascade);
> + setup_irq(MIPS_CPU_IRQ_BASE+GOLDFISH_CPU_IRQ_FIQ, &cascade);
The problem here is that you're mixing HW interrupt numbers (the VI
stuff) and things that should never be a HW interrupt number.
> +
> + goldfish_pic_domain = irq_domain_add_linear(node, GOLDFISH_NR_IRQS,
> + &irq_domain_ops, 0);
And if you're going to confuse irq and hwirq, this is definitely not the
irqdomain you want, but a legacy domain instead.
> + if (!goldfish_pic_domain)
> + panic("Failed to add IRQ domain");
> +
> + return 0;
> +}
> +
> +IRQCHIP_DECLARE(google_goldfish_pic, "google,goldfish-pic",
> + goldfish_pic_of_init);
>
As it stands, this needs a major amount of reworking. You're most
probably better off rewriting it from scratch instead of tinkering with
what looks like 10+ year old code...
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 02/10] MIPS: ranchu: Add Goldfish RTC driver |
| Message-ID | <tXnHs-AC-35@gated-at.bofh.it> |
| In reply to | #1676888 |
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Add device driver for a virtual Goldfish RTC clock.
The driver can be built only if CONFIG_MIPS and CONFIG_GOLDFISH are
set. The compatible string used by OS for binding the driver is
defined as "google,goldfish-rtc".
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
MAINTAINERS | 1 +
drivers/rtc/Kconfig | 6 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-goldfish.c | 136 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 144 insertions(+)
create mode 100644 drivers/rtc/rtc-goldfish.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 519cdef..26a1267 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -845,6 +845,7 @@ ANDROID GOLDFISH RTC DRIVER
M: Miodrag Dinic <miodrag.dinic@imgtec.com>
S: Supported
F: Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
+F: drivers/rtc/rtc-goldfish.c
ANDROID ION DRIVER
M: Laura Abbott <labbott@redhat.com>
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 8d3b957..510c5b7 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1753,5 +1753,11 @@ config RTC_DRV_HID_SENSOR_TIME
If this driver is compiled as a module, it will be named
rtc-hid-sensor-time.
+config RTC_DRV_GOLDFISH
+ tristate "Goldfish Real Time Clock"
+ depends on MIPS
+ depends on GOLDFISH
+ help
+ Say yes here to build support for the Goldfish RTC.
endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 13857d2..dfc38f5 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -168,3 +168,4 @@ obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o
obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
obj-$(CONFIG_RTC_DRV_XGENE) += rtc-xgene.o
obj-$(CONFIG_RTC_DRV_ZYNQMP) += rtc-zynqmp.o
+obj-$(CONFIG_RTC_DRV_GOLDFISH) += rtc-goldfish.o
diff --git a/drivers/rtc/rtc-goldfish.c b/drivers/rtc/rtc-goldfish.c
new file mode 100644
index 0000000..e206a98
--- /dev/null
+++ b/drivers/rtc/rtc-goldfish.c
@@ -0,0 +1,136 @@
+/* drivers/rtc/rtc-goldfish.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (C) 2017 Imagination Technologies Ltd.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+
+#define TIMER_TIME_LOW 0x00 /* get low bits of current time */
+ /* and update TIMER_TIME_HIGH */
+#define TIMER_TIME_HIGH 0x04 /* get high bits of time at last */
+ /* TIMER_TIME_LOW read */
+#define TIMER_ALARM_LOW 0x08 /* set low bits of alarm and */
+ /* activate it */
+#define TIMER_ALARM_HIGH 0x0c /* set high bits of next alarm */
+#define TIMER_CLEAR_INTERRUPT 0x10
+#define TIMER_CLEAR_ALARM 0x14
+
+struct goldfish_rtc {
+ void __iomem *base;
+ u32 irq;
+ struct rtc_device *rtc;
+};
+
+static irqreturn_t goldfish_rtc_interrupt(int irq, void *dev_id)
+{
+ struct goldfish_rtc *qrtc = dev_id;
+ unsigned long events = 0;
+ void __iomem *base = qrtc->base;
+
+ writel(1, base + TIMER_CLEAR_INTERRUPT);
+ events = RTC_IRQF | RTC_AF;
+
+ rtc_update_irq(qrtc->rtc, 1, events);
+
+ return IRQ_HANDLED;
+}
+
+static int goldfish_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ u64 time;
+ u64 time_low;
+ u64 time_high;
+ u64 time_high_prev;
+
+ struct goldfish_rtc *qrtc =
+ platform_get_drvdata(to_platform_device(dev));
+ void __iomem *base = qrtc->base;
+
+ time_high = readl(base + TIMER_TIME_HIGH);
+ do {
+ time_high_prev = time_high;
+ time_low = readl(base + TIMER_TIME_LOW);
+ time_high = readl(base + TIMER_TIME_HIGH);
+ } while (time_high != time_high_prev);
+ time = (time_high << 32) | time_low;
+
+ do_div(time, NSEC_PER_SEC);
+
+ rtc_time_to_tm(time, tm);
+
+ return 0;
+}
+
+static const struct rtc_class_ops goldfish_rtc_ops = {
+ .read_time = goldfish_rtc_read_time,
+};
+
+static int goldfish_rtc_probe(struct platform_device *pdev)
+{
+ struct resource *r;
+ struct goldfish_rtc *qrtc;
+ unsigned long rtc_dev_len;
+ unsigned long rtc_dev_addr;
+ int err;
+
+ qrtc = devm_kzalloc(&pdev->dev, sizeof(*qrtc), GFP_KERNEL);
+ if (qrtc == NULL)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, qrtc);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (r == NULL)
+ return -ENODEV;
+
+ rtc_dev_addr = r->start;
+ rtc_dev_len = resource_size(r);
+ qrtc->base = devm_ioremap(&pdev->dev, rtc_dev_addr, rtc_dev_len);
+ if (IS_ERR(qrtc->base))
+ return -ENODEV;
+
+ qrtc->irq = platform_get_irq(pdev, 0);
+ if (qrtc->irq < 0)
+ return -ENODEV;
+
+ qrtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
+ &goldfish_rtc_ops, THIS_MODULE);
+ if (IS_ERR(qrtc->rtc))
+ return PTR_ERR(qrtc->rtc);
+
+ err = devm_request_irq(&pdev->dev, qrtc->irq, goldfish_rtc_interrupt,
+ 0, pdev->name, qrtc);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static const struct of_device_id goldfish_rtc_of_match[] = {
+ { .compatible = "google,goldfish-rtc", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, goldfish_rtc_of_match);
+
+static struct platform_driver goldfish_rtc = {
+ .probe = goldfish_rtc_probe,
+ .driver = {
+ .name = "goldfish_rtc",
+ .of_match_table = goldfish_rtc_of_match,
+ }
+};
+
+module_platform_driver(goldfish_rtc);
--
2.7.4
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| From | Aleksandar Markovic <aleksandar.markovic@rt-rk.com> |
|---|---|
| Date | 2017-06-28 18:10 +0200 |
| Subject | [PATCH v2 01/10] Documentation: Add device tree binding for Goldfish RTC driver |
| Message-ID | <tXnHs-AC-37@gated-at.bofh.it> |
| In reply to | #1676888 |
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Add documentation for DT binding of Goldfish RTC driver. The compatible
string used by OS for binding the driver is "google,goldfish-rtc".
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
.../devicetree/bindings/rtc/google,goldfish-rtc.txt | 17 +++++++++++++++++
MAINTAINERS | 5 +++++
2 files changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
diff --git a/Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt b/Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
new file mode 100644
index 0000000..634312d
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
@@ -0,0 +1,17 @@
+Android Goldfish RTC
+
+Android Goldfish RTC device used by Android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-rtc"
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish_timer@9020000 {
+ compatible = "google,goldfish-rtc";
+ reg = <0x9020000 0x1000>;
+ interrupts = <0x3>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 09b5ab6..519cdef 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -841,6 +841,11 @@ S: Supported
F: drivers/android/
F: drivers/staging/android/
+ANDROID GOLDFISH RTC DRIVER
+M: Miodrag Dinic <miodrag.dinic@imgtec.com>
+S: Supported
+F: Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
+
ANDROID ION DRIVER
M: Laura Abbott <labbott@redhat.com>
M: Sumit Semwal <sumit.semwal@linaro.org>
--
2.7.4
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