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Groups > linux.kernel > #1677644 > unrolled thread
| Started by | Claudiu Beznea <claudiu.beznea@microchip.com> |
|---|---|
| First post | 2017-06-29 13:50 +0200 |
| Last post | 2017-06-29 13:50 +0200 |
| Articles | 2 — 1 participant |
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[PATCH 0/5] Add SoM1 support Claudiu Beznea <claudiu.beznea@microchip.com> - 2017-06-29 13:50 +0200
[PATCH 2/5] ARM: dts: at91: sama5d2: add isc node Claudiu Beznea <claudiu.beznea@microchip.com> - 2017-06-29 13:50 +0200
| From | Claudiu Beznea <claudiu.beznea@microchip.com> |
|---|---|
| Date | 2017-06-29 13:50 +0200 |
| Subject | [PATCH 0/5] Add SoM1 support |
| Message-ID | <tXG7n-71O-5@gated-at.bofh.it> |
Hi all, This series adds support for sama5d2 SoM1 devices. The at91-sama5d27_som1.dtsi add specific bindings for SoM1 board. The at91-sama5d27_som1_ek.dts add specific bindings for SoM1 EK board. The sama5d27_som1_ek uses a EEPROM binding, "start-offset", which is introduced in patch series: "[RFC PATCH 0/3] Add at24 functionality to read form different EEPROM offsets". Thank you, Claudiu Claudiu Beznea (2): ARM: dts: at91: at91-sama5d27_som1: add sama5d27 SoM1 support ARM: dts: sama5d27_som1_ek: Add sama5d27 SoM1 EK support Cristian Birsan (1): drivers: soc: atmel: Add basic support for new sama5d2 SiPs Cyrille Pitchen (1): ARM: dts: at91: sama5d2: add QSPI nodes Songjun Wu (1): ARM: dts: at91: sama5d2: add isc node arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 178 +++++++++ arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 551 ++++++++++++++++++++++++++++ arch/arm/boot/dts/sama5d2.dtsi | 38 ++ drivers/soc/atmel/soc.c | 8 + drivers/soc/atmel/soc.h | 4 + 6 files changed, 780 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d27_som1.dtsi create mode 100644 arch/arm/boot/dts/at91-sama5d27_som1_ek.dts -- 2.7.4
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| From | Claudiu Beznea <claudiu.beznea@microchip.com> |
|---|---|
| Date | 2017-06-29 13:50 +0200 |
| Subject | [PATCH 2/5] ARM: dts: at91: sama5d2: add isc node |
| Message-ID | <tXG7o-71O-23@gated-at.bofh.it> |
| In reply to | #1677644 |
From: Songjun Wu <songjun.wu@microchip.com>
Add isc node, it conflicts with pdmic and uart3.
Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
[claudiu.beznea@microchip.com: place isc node after hlcdc node]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 71e9d83..9d13b55 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -416,6 +416,17 @@
};
};
+ isc: isc@f0008000 {
+ compatible = "atmel,sama5d2-isc";
+ reg = <0xf0008000 0x4000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
+ clock-names = "hclock", "iscck", "gck";
+ #clock-cells = <0>;
+ clock-output-names = "isc-mck";
+ status = "disabled";
+ };
+
ramc0: ramc@f000c000 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xf000c000 0x200>;
@@ -925,6 +936,11 @@
atmel,clk-output-range = <0 83000000>;
};
+ isc_gclk: isc_gclk {
+ #clock-cells = <0>;
+ reg = <46>;
+ };
+
pdmic_gclk: pdmic_gclk {
#clock-cells = <0>;
reg = <48>;
--
2.7.4
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