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Groups > linux.kernel > #1677471 > unrolled thread

[PATCH 00/14] Add QCOM QPIC NAND support

Started byAbhishek Sahu <absahu@codeaurora.org>
First post2017-06-29 09:20 +0200
Last post2017-06-29 09:30 +0200
Articles 6 — 4 participants

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Contents

  [PATCH 00/14] Add QCOM QPIC NAND support Abhishek Sahu <absahu@codeaurora.org> - 2017-06-29 09:20 +0200
    [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Abhishek Sahu <absahu@codeaurora.org> - 2017-06-29 09:20 +0200
      Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Marek Vasut <marek.vasut@gmail.com> - 2017-06-29 11:50 +0200
      Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Archit Taneja <architt@codeaurora.org> - 2017-07-03 06:40 +0200
      Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA Sricharan R <sricharan@codeaurora.org> - 2017-07-03 08:30 +0200
    [PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing Abhishek Sahu <absahu@codeaurora.org> - 2017-06-29 09:30 +0200

#1677471 — [PATCH 00/14] Add QCOM QPIC NAND support

FromAbhishek Sahu <absahu@codeaurora.org>
Date2017-06-29 09:20 +0200
Subject[PATCH 00/14] Add QCOM QPIC NAND support
Message-ID<tXBU5-4BD-3@gated-at.bofh.it>
The current QCOM NAND driver only support EBI2 NAND which uses
ADM DMA. The latest QCOM controller supports QPIC NAND which uses
BAM DMA. NAND registers and programming sequence are same for EBI2
and QPIC NAND so the same driver can support QPIC NAND also by
adding the BAM DMA support. This patch series adds the support for
QPIC NAND controller version 1.4.0 available in IPQ4019 and QPIC
NAND controller version 1.5.0 available in IPQ8074.

The kernel MTD tests have been run to validate all these patches
in IPQ8064 AP148, IPQ4019 DK04 and IPQ8074 HK01 boards and all
the MTD tests are passing on these boards.

The QPIC NAND requires the command channel support for BAM DMA
engine and currently BAM engine does not support the command
descriptors so the following patches have been posted for the
same in dmaengine mailing list. The above patches are dependent
upon these BAM DMA patches.

https://www.spinics.net/lists/kernel/msg2542483.html

Abhishek Sahu (14):
  qcom: mtd: nand: Add driver data for QPIC DMA
  qcom: mtd: nand: add and initialize QPIC DMA resources
  qcom: mtd: nand: Fixed config error for BCH
  qcom: mtd: nand: reorganize nand devices probing
  qcom: mtd: nand: allocate bam transaction
  qcom: mtd: nand: add bam dma descriptor handling
  qcom: mtd: nand: support for passing flags in transfer functions
  qcom: mtd: nand: Add support for additional CSRs
  qcom: mtd: nand: BAM support for read page
  qcom: mtd: nand: support for QPIC Page read/write
  qcom: mtd: nand: BAM raw read and write support
  qcom: mtd: nand: change register offset defines with enums
  qcom: mtd: nand: support for QPIC version 1.5.0
  qcom: mtd: nand: programmed NAND_DEV_CMD_VLD register

 .../devicetree/bindings/mtd/qcom_nandc.txt         |  110 +-
 drivers/mtd/nand/qcom_nandc.c                      | 1114 +++++++++++++++++---
 2 files changed, 1050 insertions(+), 174 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

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#1677474 — [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

FromAbhishek Sahu <absahu@codeaurora.org>
Date2017-06-29 09:20 +0200
Subject[PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA
Message-ID<tXBU8-4BD-41@gated-at.bofh.it>
In reply to#1677471
The current driver only support EBI2 NAND which uses ADM DMA. The
latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
registers and programming sequence are same for EBI2 and QPIC
NAND so the same driver can support QPIC NAND also by adding the
BAM DMA support. This patch adds the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
 drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
 2 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 70dd511..5d0f7ae 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,7 +1,9 @@
 * Qualcomm NAND controller
 
 Required properties:
-- compatible:		should be "qcom,ipq806x-nand"
+- compatible:		must be one of the following:
+	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
+	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
 - clock-names:		must contain "core" for the core clock and "aon" for the
@@ -84,3 +86,40 @@ nand@1ac00000 {
 		};
 	};
 };
+
+nand@79b0000 {
+	compatible = "qcom,qpic-nandc-v1.4.0";
+	reg = <0x79b0000 0x1000>;
+
+	clocks = <&gcc GCC_QPIC_CLK>,
+		<&gcc GCC_QPIC_AHB_CLK>;
+	clock-names = "core", "aon";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "qcom,nandcs";
+		reg = <0>;
+
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot-nand";
+				reg = <0 0x58a0000>;
+			};
+
+			partition@58a0000 {
+				label = "fs-nand";
+				reg = <0x58a0000 0x4000000>;
+			};
+		};
+	};
+};
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 57d483a..f55f728 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -234,6 +234,8 @@ struct nandc_regs {
  * @cmd1/vld:			some fixed controller register values
  * @ecc_modes:			supported ECC modes by the current controller,
  *				initialized via DT match data
+ * @dma_bam_enabled:		flag to tell whether nand controller is using
+ *				bam dma
  */
 struct qcom_nand_controller {
 	struct nand_hw_control controller;
@@ -253,6 +255,7 @@ struct qcom_nand_controller {
 	struct list_head desc_list;
 
 	u8		*data_buffer;
+	bool		dma_bam_enabled;
 	int		buf_size;
 	int		buf_count;
 	int		buf_start;
@@ -316,6 +319,17 @@ struct qcom_nand_host {
 	u32 clrreadstatus;
 };
 
+/*
+ * This data type corresponds to the nand driver data which will be used at
+ * driver probe time
+ * @ecc_modes - ecc mode for nand
+ * @dma_bam_enabled - whether this driver is using bam
+ */
+struct qcom_nand_driver_data {
+	u32 ecc_modes;
+	bool dma_bam_enabled;
+};
+
 static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
 {
 	return container_of(chip, struct qcom_nand_host, chip);
@@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	struct device_node *dn = dev->of_node, *child;
 	struct resource *res;
 	int ret;
+	const struct qcom_nand_driver_data *driver_data;
 
 	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
 	if (!nandc)
@@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	nandc->ecc_modes = (unsigned long)dev_data;
+	driver_data = (const struct qcom_nand_driver_data *)dev_data;
+
+	nandc->ecc_modes = driver_data->ecc_modes;
+	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	nandc->base = devm_ioremap_resource(dev, res);
@@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
 
+static const struct qcom_nand_driver_data ebi2_nandc_data = {
+	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = false,
+};
+
+static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
+	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
+	.dma_bam_enabled = true,
+};
 /*
  * data will hold a struct pointer containing more differences once we support
  * more controller variants
  */
 static const struct of_device_id qcom_nandc_of_match[] = {
 	{	.compatible = "qcom,ipq806x-nand",
-		.data = (void *)EBI2_NANDC_ECC_MODES,
+		.data = (void *)&ebi2_nandc_data,
+	},
+	{	.compatible = "qcom,qpic-nandc-v1.4.0",
+		.data = (void *)&qpic_nandc_v1_4_0_data,
 	},
 	{}
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

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#1677565 — Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

FromMarek Vasut <marek.vasut@gmail.com>
Date2017-06-29 11:50 +0200
SubjectRe: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA
Message-ID<tXEfg-5VQ-15@gated-at.bofh.it>
In reply to#1677474
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>

Split this into DT bindings patch and code patch ...

> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
>  drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
>  2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..5d0f7ae 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
>  * Qualcomm NAND controller
>  
>  Required properties:
> -- compatible:		should be "qcom,ipq806x-nand"
> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>  - reg:			MMIO address range
>  - clocks:		must contain core clock and always on clock
>  - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -84,3 +86,40 @@ nand@1ac00000 {
>  		};
>  	};
>  };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..f55f728 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>   *
>   * This software is licensed under the terms of the GNU General Public
>   * License version 2, as published by the Free Software Foundation, and
> @@ -234,6 +234,8 @@ struct nandc_regs {
>   * @cmd1/vld:			some fixed controller register values
>   * @ecc_modes:			supported ECC modes by the current controller,
>   *				initialized via DT match data
> + * @dma_bam_enabled:		flag to tell whether nand controller is using
> + *				bam dma
>   */
>  struct qcom_nand_controller {
>  	struct nand_hw_control controller;
> @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> +	bool		dma_bam_enabled;
>  	int		buf_size;
>  	int		buf_count;
>  	int		buf_start;
> @@ -316,6 +319,17 @@ struct qcom_nand_host {
>  	u32 clrreadstatus;
>  };
>  
> +/*
> + * This data type corresponds to the nand driver data which will be used at
> + * driver probe time
> + * @ecc_modes - ecc mode for nand
> + * @dma_bam_enabled - whether this driver is using bam
> + */
> +struct qcom_nand_driver_data {
> +	u32 ecc_modes;
> +	bool dma_bam_enabled;
> +};
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  	struct device_node *dn = dev->of_node, *child;
>  	struct resource *res;
>  	int ret;
> +	const struct qcom_nand_driver_data *driver_data;
>  
>  	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>  	if (!nandc)
> @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	nandc->ecc_modes = (unsigned long)dev_data;
> +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> +
> +	nandc->ecc_modes = driver_data->ecc_modes;
> +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>  
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +};
>  /*
>   * data will hold a struct pointer containing more differences once we support
>   * more controller variants
>   */
>  static const struct of_device_id qcom_nandc_of_match[] = {
>  	{	.compatible = "qcom,ipq806x-nand",
> -		.data = (void *)EBI2_NANDC_ECC_MODES,
> +		.data = (void *)&ebi2_nandc_data,
> +	},
> +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> +		.data = (void *)&qpic_nandc_v1_4_0_data,
>  	},
>  	{}
>  };
> 


-- 
Best regards,
Marek Vasut

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#1679638 — Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

FromArchit Taneja <architt@codeaurora.org>
Date2017-07-03 06:40 +0200
SubjectRe: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA
Message-ID<tZ1jr-4q7-1@gated-at.bofh.it>
In reply to#1677474

On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>   .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
>   drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
>   2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..5d0f7ae 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
>   * Qualcomm NAND controller
>   
>   Required properties:
> -- compatible:		should be "qcom,ipq806x-nand"

Since you're changing the compatible string, could you mention in the commit message that
it's okay to do so since there aren't any upstream dtsi files using this binding?

> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.

Are we sure that all EBI2 based NAND controllers would work by this single binding?
Should we put a version here too like we've done for QPIC?

> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>   - reg:			MMIO address range
>   - clocks:		must contain core clock and always on clock
>   - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -84,3 +86,40 @@ nand@1ac00000 {
>   		};
>   	};
>   };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..f55f728 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
>   /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>    *
>    * This software is licensed under the terms of the GNU General Public
>    * License version 2, as published by the Free Software Foundation, and
> @@ -234,6 +234,8 @@ struct nandc_regs {
>    * @cmd1/vld:			some fixed controller register values
>    * @ecc_modes:			supported ECC modes by the current controller,
>    *				initialized via DT match data
> + * @dma_bam_enabled:		flag to tell whether nand controller is using
> + *				bam dma
>    */
>   struct qcom_nand_controller {
>   	struct nand_hw_control controller;
> @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>   	struct list_head desc_list;
>   
>   	u8		*data_buffer;
> +	bool		dma_bam_enabled;
>   	int		buf_size;
>   	int		buf_count;
>   	int		buf_start;
> @@ -316,6 +319,17 @@ struct qcom_nand_host {
>   	u32 clrreadstatus;
>   };
>   
> +/*
> + * This data type corresponds to the nand driver data which will be used at
> + * driver probe time
> + * @ecc_modes - ecc mode for nand
> + * @dma_bam_enabled - whether this driver is using bam
> + */
> +struct qcom_nand_driver_data {
> +	u32 ecc_modes;
> +	bool dma_bam_enabled;
> +};
> +
>   static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>   {
>   	return container_of(chip, struct qcom_nand_host, chip);
> @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   	struct device_node *dn = dev->of_node, *child;
>   	struct resource *res;
>   	int ret;
> +	const struct qcom_nand_driver_data *driver_data;
>   
>   	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>   	if (!nandc)
> @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>   		return -ENODEV;
>   	}
>   
> -	nandc->ecc_modes = (unsigned long)dev_data;
> +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> +
> +	nandc->ecc_modes = driver_data->ecc_modes;
> +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>   
>   	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>   	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>   	return 0;
>   }
>   
> -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>   
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +};
>   /*
>    * data will hold a struct pointer containing more differences once we support
>    * more controller variants
>    */
>   static const struct of_device_id qcom_nandc_of_match[] = {
>   	{	.compatible = "qcom,ipq806x-nand",

Please make sure that you update the compatible string above too.

Thanks,
Archit

> -		.data = (void *)EBI2_NANDC_ECC_MODES,
> +		.data = (void *)&ebi2_nandc_data,
> +	},
> +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> +		.data = (void *)&qpic_nandc_v1_4_0_data,
>   	},
>   	{}
>   };
> 

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#1679665 — Re: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA

FromSricharan R <sricharan@codeaurora.org>
Date2017-07-03 08:30 +0200
SubjectRe: [PATCH 01/14] qcom: mtd: nand: Add driver data for QPIC DMA
Message-ID<tZ31U-5Fr-17@gated-at.bofh.it>
In reply to#1677474
Hi Abhishek,

On 6/29/2017 12:45 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
> registers and programming sequence are same for EBI2 and QPIC
> NAND so the same driver can support QPIC NAND also by adding the
> BAM DMA support. This patch adds the QPIC NAND support in current
> NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
> maps it with different configuration parameter in driver data.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 41 +++++++++++++++++++++-
>  drivers/mtd/nand/qcom_nandc.c                      | 37 ++++++++++++++++---
>  2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index 70dd511..5d0f7ae 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,7 +1,9 @@
>  * Qualcomm NAND controller
>  
>  Required properties:
> -- compatible:		should be "qcom,ipq806x-nand"
> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>  - reg:			MMIO address range
>  - clocks:		must contain core clock and always on clock
>  - clock-names:		must contain "core" for the core clock and "aon" for the
> @@ -84,3 +86,40 @@ nand@1ac00000 {
>  		};
>  	};
>  };
> +
> +nand@79b0000 {
> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {
> +		compatible = "qcom,nandcs";
> +		reg = <0>;
> +
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 57d483a..f55f728 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>   *
>   * This software is licensed under the terms of the GNU General Public
>   * License version 2, as published by the Free Software Foundation, and
> @@ -234,6 +234,8 @@ struct nandc_regs {
>   * @cmd1/vld:			some fixed controller register values
>   * @ecc_modes:			supported ECC modes by the current controller,
>   *				initialized via DT match data
> + * @dma_bam_enabled:		flag to tell whether nand controller is using
> + *				bam dma
>   */

 simply is_bam ?

>  struct qcom_nand_controller {
>  	struct nand_hw_control controller;
> @@ -253,6 +255,7 @@ struct qcom_nand_controller {
>  	struct list_head desc_list;
>  
>  	u8		*data_buffer;
> +	bool		dma_bam_enabled;
>  	int		buf_size;
>  	int		buf_count;
>  	int		buf_start;
> @@ -316,6 +319,17 @@ struct qcom_nand_host {
>  	u32 clrreadstatus;
>  };
>  
> +/*
> + * This data type corresponds to the nand driver data which will be used at
> + * driver probe time
> + * @ecc_modes - ecc mode for nand
> + * @dma_bam_enabled - whether this driver is using bam
> + */
> +struct qcom_nand_driver_data {
> +	u32 ecc_modes;
> +	bool dma_bam_enabled;
> +};
> +
>  static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>  {
>  	return container_of(chip, struct qcom_nand_host, chip);
> @@ -2073,6 +2087,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  	struct device_node *dn = dev->of_node, *child;
>  	struct resource *res;
>  	int ret;
> +	const struct qcom_nand_driver_data *driver_data;

  Directly assign of the of_device_match_data here and avoid additional variable, cast.

Regards,
 Sricharan



>  
>  	nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
>  	if (!nandc)
> @@ -2087,7 +2102,10 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	nandc->ecc_modes = (unsigned long)dev_data;
> +	driver_data = (const struct qcom_nand_driver_data *)dev_data;
> +
> +	nandc->ecc_modes = driver_data->ecc_modes;
> +	nandc->dma_bam_enabled = driver_data->dma_bam_enabled;
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>  	nandc->base = devm_ioremap_resource(dev, res);
> @@ -2179,15 +2197,26 @@ static int qcom_nandc_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -#define EBI2_NANDC_ECC_MODES	(ECC_RS_4BIT | ECC_BCH_8BIT)
>  
> +static const struct qcom_nand_driver_data ebi2_nandc_data = {
> +	.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = false,
> +};
> +
> +static const struct qcom_nand_driver_data qpic_nandc_v1_4_0_data = {
> +	.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> +	.dma_bam_enabled = true,
> +};
>  /*
>   * data will hold a struct pointer containing more differences once we support
>   * more controller variants
>   */
>  static const struct of_device_id qcom_nandc_of_match[] = {
>  	{	.compatible = "qcom,ipq806x-nand",
> -		.data = (void *)EBI2_NANDC_ECC_MODES,
> +		.data = (void *)&ebi2_nandc_data,
> +	},
> +	{	.compatible = "qcom,qpic-nandc-v1.4.0",
> +		.data = (void *)&qpic_nandc_v1_4_0_data,
>  	},
>  	{}
>  };
> 

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#1677483 — [PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing

FromAbhishek Sahu <absahu@codeaurora.org>
Date2017-06-29 09:30 +0200
Subject[PATCH 04/14] qcom: mtd: nand: reorganize nand devices probing
Message-ID<tXC3N-4EX-35@gated-at.bofh.it>
In reply to#1677471
This is reorganization of exiting code and will not change any
functionality. The NAND controller supports multiple NAND device
with different page size. The subsequent patch allocate memory
which depends upon the maximum number of codewords so this patch
reorganizes the NAND device probing. First the ONFI parameter
page will be read from each connected device followed by MTD
device registration.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/mtd/nand/qcom_nandc.c | 92 ++++++++++++++++++++++++++++---------------
 1 file changed, 61 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 410ee53..eb0ec19 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
@@ -2102,14 +2102,69 @@ static int qcom_nand_host_init(struct qcom_nand_controller *nandc,
 		return ret;
 
 	ret = qcom_nand_host_setup(host);
-	if (ret)
-		return ret;
+
+	return ret;
+}
+
+static int qcom_nand_mtd_register(struct qcom_nand_controller *nandc,
+				  struct qcom_nand_host *host,
+				  struct device_node *dn)
+{
+	struct nand_chip *chip = &host->chip;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	int ret;
 
 	ret = nand_scan_tail(mtd);
 	if (ret)
 		return ret;
 
-	return mtd_device_register(mtd, NULL, 0);
+	ret = mtd_device_register(mtd, NULL, 0);
+	if (ret)
+		nand_cleanup(mtd_to_nand(mtd));
+
+	return ret;
+}
+
+static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc)
+{
+	struct device *dev = nandc->dev;
+	struct device_node *dn = dev->of_node, *child;
+	struct qcom_nand_host *host, *tmp;
+	int ret;
+
+	for_each_available_child_of_node(dn, child) {
+		if (of_device_is_compatible(child, "qcom,nandcs")) {
+			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+			if (!host) {
+				of_node_put(child);
+				return -ENOMEM;
+			}
+
+			ret = qcom_nand_host_init(nandc, host, child);
+			if (ret) {
+				devm_kfree(dev, host);
+				continue;
+			}
+
+			list_add_tail(&host->node, &nandc->host_list);
+		}
+	}
+
+	if (list_empty(&nandc->host_list))
+		return -ENODEV;
+
+	list_for_each_entry_safe(host, tmp, &nandc->host_list, node) {
+		ret = qcom_nand_mtd_register(nandc, host, child);
+		if (ret) {
+			list_del(&host->node);
+			devm_kfree(dev, host);
+		}
+	}
+
+	if (list_empty(&nandc->host_list))
+		return -ENODEV;
+
+	return 0;
 }
 
 /* parse custom DT properties here */
@@ -2141,10 +2196,8 @@ static int qcom_nandc_parse_dt(struct platform_device *pdev)
 static int qcom_nandc_probe(struct platform_device *pdev)
 {
 	struct qcom_nand_controller *nandc;
-	struct qcom_nand_host *host;
 	const void *dev_data;
 	struct device *dev = &pdev->dev;
-	struct device_node *dn = dev->of_node, *child;
 	struct resource *res;
 	int ret;
 	const struct qcom_nand_driver_data *driver_data;
@@ -2202,35 +2255,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_setup;
 
-	for_each_available_child_of_node(dn, child) {
-		if (of_device_is_compatible(child, "qcom,nandcs")) {
-			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
-			if (!host) {
-				of_node_put(child);
-				ret = -ENOMEM;
-				goto err_cs_init;
-			}
-
-			ret = qcom_nand_host_init(nandc, host, child);
-			if (ret) {
-				devm_kfree(dev, host);
-				continue;
-			}
-
-			list_add_tail(&host->node, &nandc->host_list);
-		}
-	}
-
-	if (list_empty(&nandc->host_list)) {
-		ret = -ENODEV;
-		goto err_cs_init;
-	}
+	ret = qcom_probe_nand_devices(nandc);
+	if (ret)
+		goto err_setup;
 
 	return 0;
 
-err_cs_init:
-	list_for_each_entry(host, &nandc->host_list, node)
-		nand_release(nand_to_mtd(&host->chip));
 err_setup:
 	clk_disable_unprepare(nandc->aon_clk);
 err_aon_clk:
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