Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1672577 > unrolled thread
| Started by | Ding Tianhong <dingtianhong@huawei.com> |
|---|---|
| First post | 2017-06-22 14:20 +0200 |
| Last post | 2017-06-29 07:50 +0200 |
| Articles | 3 — 1 participant |
Back to article view | Back to linux.kernel
[PATCH v6 0/3] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-06-22 14:20 +0200
[PATCH v6 2/3] PCI: Enable PCIe Relaxed Ordering if supported Ding Tianhong <dingtianhong@huawei.com> - 2017-06-22 14:20 +0200
Re: [PATCH v6 0/3] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong <dingtianhong@huawei.com> - 2017-06-29 07:50 +0200
| From | Ding Tianhong <dingtianhong@huawei.com> |
|---|---|
| Date | 2017-06-22 14:20 +0200 |
| Subject | [PATCH v6 0/3] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag |
| Message-ID | <tV9fz-4zM-5@gated-at.bofh.it> |
Some devices have problems with Transaction Layer Packets with the Relaxed
Ordering Attribute set. This patch set adds a new PCIe Device Flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
devices with Relaxed Ordering issues, and a use of this new flag by the
cxgb4 driver to avoid using Relaxed Ordering with problematic Root Complex
Ports.
It's been years since I've submitted kernel.org patches, I appolgise for the
almost certain submission errors.
v2: Alexander point out that the v1 was only a part of the whole solution,
some platform which has some issues could use the new flag to indicate
that it is not safe to enable relaxed ordering attribute, then we need
to clear the relaxed ordering enable bits in the PCI configuration when
initializing the device. So add a new second patch to modify the PCI
initialization code to clear the relaxed ordering enable bit in the
event that the root complex doesn't want relaxed ordering enabled.
The third patch was base on the v1's second patch and only be changed
to query the relaxed ordering enable bit in the PCI configuration space
to allow the Chelsio NIC to send TLPs with the relaxed ordering attributes
set.
This version didn't plan to drop the defines for Intel Drivers to use the
new checking way to enable relaxed ordering because it is not the hardest
part of the moment, we could fix it in next patchset when this patches
reach the goal.
v3: Redesigned the logic for pci_configure_relaxed_ordering when configuration,
If a PCIe device didn't enable the relaxed ordering attribute default,
we should not do anything in the PCIe configuration, otherwise we
should check if any of the devices above us do not support relaxed
ordering by the PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag, then base on
the result if we get a return that indicate that the relaxed ordering
is not supported we should update our device to disable relaxed ordering
in configuration space. If the device above us doesn't exist or isn't
the PCIe device, we shouldn't do anything and skip updating relaxed ordering
because we are probably running in a guest.
v4: Rename the functions pcie_get_relaxed_ordering and pcie_disable_relaxed_ordering
according John's suggestion, and modify the description, use the true/false
as the return value.
We shouldn't enable relaxed ordering attribute by the setting in the root
complex configuration space for PCIe device, so fix it for cxgb4.
Fix some format issues.
v5: Removed the unnecessary code for some function which only return the bool
value, and add the check for VF device.
Make this patch set base on 4.12-rc5.
v6: Fix the logic error in the need to enable the relaxed ordering attribute for cxgb4.
Casey Leedom (2):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (1):
PCI: Enable PCIe Relaxed Ordering if supported
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 ++++++++++
drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 +--
drivers/pci/pci.c | 32 +++++++++++++++++++
drivers/pci/probe.c | 41 +++++++++++++++++++++++++
drivers/pci/quirks.c | 38 +++++++++++++++++++++++
include/linux/pci.h | 4 +++
7 files changed, 136 insertions(+), 2 deletions(-)
--
1.9.0
[toc] | [next] | [standalone]
| From | Ding Tianhong <dingtianhong@huawei.com> |
|---|---|
| Date | 2017-06-22 14:20 +0200 |
| Subject | [PATCH v6 2/3] PCI: Enable PCIe Relaxed Ordering if supported |
| Message-ID | <tV9fA-4zM-21@gated-at.bofh.it> |
| In reply to | #1672577 |
The PCIe Device Control Register use the bit 4 to indicate that
whether the device is permitted to enable relaxed ordering or not.
But relaxed ordering is not safe for some platform which could only
use strong write ordering, so devices are allowed (but not required)
to enable relaxed ordering bit by default.
If a PCIe device didn't enable the relaxed ordering attribute default,
we should not do anything in the PCIe configuration, otherwise we
should check if any of the devices above us do not support relaxed
ordering by the PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag, then base on
the result if we get a return that indicate that the relaxed ordering
is not supported we should update our device to disable relaxed ordering
in configuration space. If the device above us doesn't exist or isn't
the PCIe device, we shouldn't do anything and skip updating relaxed ordering
because we are probably running in a guest machine.
Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>
---
drivers/pci/pci.c | 29 +++++++++++++++++++++++++++++
drivers/pci/probe.c | 37 +++++++++++++++++++++++++++++++++++++
include/linux/pci.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 563901c..c773e0d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4879,6 +4879,35 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
EXPORT_SYMBOL(pcie_set_mps);
/**
+ * pcie_clear_relaxed_ordering - clear PCI Express relaxed ordering bit
+ * @dev: PCI device to query
+ *
+ * If possible clear relaxed ordering
+ */
+int pcie_clear_relaxed_ordering(struct pci_dev *dev)
+{
+ return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
+ PCI_EXP_DEVCTL_RELAX_EN);
+}
+EXPORT_SYMBOL(pcie_clear_relaxed_ordering);
+
+/**
+ * pcie_relaxed_ordering_supported - Probe for PCIe relexed ordering support
+ * @dev: PCI device to query
+ *
+ * Returns true if the device support relaxed ordering attribute.
+ */
+bool pcie_relaxed_ordering_supported(struct pci_dev *dev)
+{
+ u16 v;
+
+ pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
+
+ return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
+}
+EXPORT_SYMBOL(pcie_relaxed_ordering_supported);
+
+/**
* pcie_get_minimum_link - determine minimum link settings of a PCI device
* @dev: PCI device to query
* @speed: storage for minimum speed
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 19c8950..2615299 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1701,6 +1701,42 @@ static void pci_configure_extended_tags(struct pci_dev *dev)
PCI_EXP_DEVCTL_EXT_TAG);
}
+/**
+ * pci_dev_should_disable_relaxed_ordering - check if the PCI device
+ * should disable the relaxed ordering attribute.
+ * @dev: PCI device
+ *
+ * Return true if any of the PCI devices above us do not support
+ * relaxed ordering.
+ */
+static bool pci_dev_should_disable_relaxed_ordering(struct pci_dev *dev)
+{
+ while (dev) {
+ if (dev->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING)
+ return true;
+
+ dev = dev->bus->self;
+ }
+
+ return false;
+}
+
+static void pci_configure_relaxed_ordering(struct pci_dev *dev)
+{
+ /* We should not alter the relaxed ordering bit for the VF */
+ if (dev->is_virtfn)
+ return;
+
+ /* If the releaxed ordering enable bit is not set, do nothing. */
+ if (!pcie_relaxed_ordering_supported(dev))
+ return;
+
+ if (pci_dev_should_disable_relaxed_ordering(dev)) {
+ pcie_clear_relaxed_ordering(dev);
+ dev_info(&dev->dev, "Disable Relaxed Ordering\n");
+ }
+}
+
static void pci_configure_device(struct pci_dev *dev)
{
struct hotplug_params hpp;
@@ -1708,6 +1744,7 @@ static void pci_configure_device(struct pci_dev *dev)
pci_configure_mps(dev);
pci_configure_extended_tags(dev);
+ pci_configure_relaxed_ordering(dev);
memset(&hpp, 0, sizeof(hpp));
ret = pci_get_hp_params(dev, &hpp);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index ce77690..f5f200f 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1110,6 +1110,8 @@ int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
void pci_pme_wakeup_bus(struct pci_bus *bus);
void pci_d3cold_enable(struct pci_dev *dev);
void pci_d3cold_disable(struct pci_dev *dev);
+int pcie_clear_relaxed_ordering(struct pci_dev *dev);
+bool pcie_relaxed_ordering_supported(struct pci_dev *dev);
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
bool enable)
--
1.9.0
[toc] | [prev] | [next] | [standalone]
| From | Ding Tianhong <dingtianhong@huawei.com> |
|---|---|
| Date | 2017-06-29 07:50 +0200 |
| Message-ID | <tXAv0-3Ao-9@gated-at.bofh.it> |
| In reply to | #1672577 |
ping On 2017/6/22 20:15, Ding Tianhong wrote: > Some devices have problems with Transaction Layer Packets with the Relaxed > Ordering Attribute set. This patch set adds a new PCIe Device Flag, > PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known > devices with Relaxed Ordering issues, and a use of this new flag by the > cxgb4 driver to avoid using Relaxed Ordering with problematic Root Complex > Ports. > > It's been years since I've submitted kernel.org patches, I appolgise for the > almost certain submission errors. > > v2: Alexander point out that the v1 was only a part of the whole solution, > some platform which has some issues could use the new flag to indicate > that it is not safe to enable relaxed ordering attribute, then we need > to clear the relaxed ordering enable bits in the PCI configuration when > initializing the device. So add a new second patch to modify the PCI > initialization code to clear the relaxed ordering enable bit in the > event that the root complex doesn't want relaxed ordering enabled. > > The third patch was base on the v1's second patch and only be changed > to query the relaxed ordering enable bit in the PCI configuration space > to allow the Chelsio NIC to send TLPs with the relaxed ordering attributes > set. > > This version didn't plan to drop the defines for Intel Drivers to use the > new checking way to enable relaxed ordering because it is not the hardest > part of the moment, we could fix it in next patchset when this patches > reach the goal. > > v3: Redesigned the logic for pci_configure_relaxed_ordering when configuration, > If a PCIe device didn't enable the relaxed ordering attribute default, > we should not do anything in the PCIe configuration, otherwise we > should check if any of the devices above us do not support relaxed > ordering by the PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag, then base on > the result if we get a return that indicate that the relaxed ordering > is not supported we should update our device to disable relaxed ordering > in configuration space. If the device above us doesn't exist or isn't > the PCIe device, we shouldn't do anything and skip updating relaxed ordering > because we are probably running in a guest. > > v4: Rename the functions pcie_get_relaxed_ordering and pcie_disable_relaxed_ordering > according John's suggestion, and modify the description, use the true/false > as the return value. > > We shouldn't enable relaxed ordering attribute by the setting in the root > complex configuration space for PCIe device, so fix it for cxgb4. > > Fix some format issues. > > v5: Removed the unnecessary code for some function which only return the bool > value, and add the check for VF device. > > Make this patch set base on 4.12-rc5. > > v6: Fix the logic error in the need to enable the relaxed ordering attribute for cxgb4. > > Casey Leedom (2): > PCI: Add new PCIe Fabric End Node flag, > PCI_DEV_FLAGS_NO_RELAXED_ORDERING > net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag > > Ding Tianhong (1): > PCI: Enable PCIe Relaxed Ordering if supported > > drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 + > drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 ++++++++++ > drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 +-- > drivers/pci/pci.c | 32 +++++++++++++++++++ > drivers/pci/probe.c | 41 +++++++++++++++++++++++++ > drivers/pci/quirks.c | 38 +++++++++++++++++++++++ > include/linux/pci.h | 4 +++ > 7 files changed, 136 insertions(+), 2 deletions(-) >
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web