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[PATCH 0/6] add support for Sama5d2 audio PLL and enable ClassD

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  [PATCH 0/6] add support for Sama5d2 audio PLL and enable ClassD Quentin Schulz <quentin.schulz@free-electrons.com> - 2017-06-23 11:10 +0200
    [PATCH 1/6] clk: at91: clk-generated: remove useless divisor loop Quentin Schulz <quentin.schulz@free-electrons.com> - 2017-06-23 11:10 +0200
    [PATCH 5/6] clk: at91: clk-generated: make gclk determine audio_pll rate Quentin Schulz <quentin.schulz@free-electrons.com> - 2017-06-23 11:10 +0200

#1673410 — [PATCH 0/6] add support for Sama5d2 audio PLL and enable ClassD

This patch series adds support for the audio PLL and enables ClassD that
can be found in ATMEL Sama5d2 SoCs.

There are two audio PLLs (PMC and PAD) that shares the same parent (FRAC).
FRAC can output between 620 and 700MHz and only multiply the rate of its
parent. The two audio PLLs then divide the FRAC rate to best match the
asked rate.

I basically took an old patch series posted by Nicolas on December, 6th
2016[1][2][3] and the comments Boris did on the first version[4] Nicolas
sent on July, 15th 2015.

I also fixed the function used to compute the divisors, removed useless
spinlocks and added a range to the audio frac PLL to stay within vendor's
supported range. Clocks that are children of gclk (generated-clk) are now
able to propagate rate to the audio PLL clocks when needed. However, since
there is no rate locking, we enforce that classd_gclk be the only child of
audio_pll_pmc so we avoid multiple children modifiying parent's rate, and
classd driver modifying parent's rate which would impact the rate of each
of parent's children.

Thanks,
Quentin

[1] https://patchwork.kernel.org/patch/9462351/
[2] https://patchwork.kernel.org/patch/9462347/
[3] https://patchwork.kernel.org/patch/9462349/
[4] https://www.spinics.net/lists/arm-kernel/msg436120.html

Cyrille Pitchen (2):
  ARM: dts: at91: sama5d2: add classd nodes
  ARM: dts: at91: sama5d2_xplained: add pin muxing and enable classd

Nicolas Ferre (1):
  clk: at91: add audio pll clock driver

Quentin Schulz (3):
  clk: at91: clk-generated: remove useless divisor loop
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: clk-generated: make gclk determine audio_pll rate

 .../devicetree/bindings/clock/at91-clock.txt       |  10 +
 arch/arm/boot/dts/at91-sama5d2_xplained.dts        |  16 ++
 arch/arm/boot/dts/sama5d2.dtsi                     |  39 +++-
 arch/arm/mach-at91/Kconfig                         |   4 +
 drivers/clk/at91/Makefile                          |   2 +
 drivers/clk/at91/clk-audio-pll-pad.c               | 204 ++++++++++++++++++
 drivers/clk/at91/clk-audio-pll-pmc.c               | 175 +++++++++++++++
 drivers/clk/at91/clk-audio-pll.c                   | 237 +++++++++++++++++++++
 drivers/clk/at91/clk-generated.c                   |  79 +++++--
 include/linux/clk/at91_pmc.h                       |  25 +++
 sound/soc/atmel/atmel-classd.c                     |  20 +-
 11 files changed, 772 insertions(+), 39 deletions(-)
 create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c
 create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c
 create mode 100644 drivers/clk/at91/clk-audio-pll.c

-- 
2.11.0

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#1673411 — [PATCH 1/6] clk: at91: clk-generated: remove useless divisor loop

The driver requests the current clk rate of each of its parent clocks to
decide whether a clock rate is suitable or not. It does not request
determine_rate from a parent clock which could request a rate change in
parent clock (i.e. there is no parent rate propagation).

We know the rate we want (passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
 drivers/clk/at91/clk-generated.c | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 07c8f701e51c..dab7002937e6 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -124,19 +124,18 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
 		    (gck->range.max && min_rate > gck->range.max))
 			continue;
 
-		for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
-			tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
-			tmp_diff = abs(req->rate - tmp_rate);
-
-			if (best_diff < 0 || best_diff > tmp_diff) {
-				best_rate = tmp_rate;
-				best_diff = tmp_diff;
-				req->best_parent_rate = parent_rate;
-				req->best_parent_hw = parent;
-			}
-
-			if (!best_diff || tmp_rate < req->rate)
-				break;
+		div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
+		if (!div)
+			tmp_rate = parent_rate;
+		else
+			tmp_rate = parent_rate / div;
+		tmp_diff = abs(req->rate - tmp_rate);
+
+		if (best_diff < 0 || best_diff > tmp_diff) {
+			best_rate = tmp_rate;
+			best_diff = tmp_diff;
+			req->best_parent_rate = parent_rate;
+			req->best_parent_hw = parent;
 		}
 
 		if (!best_diff)
-- 
2.11.0

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#1673412 — [PATCH 5/6] clk: at91: clk-generated: make gclk determine audio_pll rate

This allows gclk to determine audio_pll rate and set the parent rate
accordingly.

However, there are multiple children clocks that could technically
change the rate of audio_pll. Since the clock rate is usually critical
for IPs, it isn't a good idea to have multiple clocks changing audio_pll
clock rate. There isn't any rate locking system for the moment, thus
we enforce that classd_gclk be the only one allowed to change audio_pll
rate. To remain consistent, we deny other clocks to be children of
audio_pll so classd_gclk altering audio_pll rate does not impact any
other device.

This needs to be re-worked once we have a rate locking system so two
clocks could be children of the same clock and be sure the clock rate
isn't changed by one or the other.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
---
 drivers/clk/at91/clk-generated.c | 41 ++++++++++++++++++++++++++++++++++------
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 6530a2e7e84d..e66ee735a569 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -26,6 +26,9 @@
 #define GENERATED_SOURCE_MAX	6
 #define GENERATED_MAX_DIV	255
 
+#define GCK_ID_CLASSD		59
+#define GCK_INDEX_DT_AUDIO_PLL	5
+
 struct clk_generated {
 	struct clk_hw hw;
 	struct regmap *regmap;
@@ -126,15 +129,14 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
 {
 	struct clk_generated *gck = to_clk_generated(hw);
 	struct clk_hw *parent = NULL;
+	struct clk_rate_request req_parent = *req;
 	long best_rate = -EINVAL;
-	unsigned long min_rate;
+	unsigned long min_rate, parent_rate;
 	int best_diff = -1;
 	int i;
+	u32 div;
 
-	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
-		u32 div;
-		unsigned long parent_rate;
-
+	for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
 		parent = clk_hw_get_parent_by_index(hw, i);
 		if (!parent)
 			continue;
@@ -150,11 +152,37 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
 		clk_generated_best_diff(req, parent, parent_rate, div,
 					&best_diff, &best_rate);
 
+		if (!best_diff)
+			break;
+	}
+
+	/*
+	 * The audio_pll rate can be modified unlike the five others clocks that
+	 * should never be altered.
+	 * The audio_pll can technically be used by multiple consumers. However,
+	 * they all are likely to want to modify its rate while the rate is
+	 * critical for each one. Since we do not have a rate locking for the
+	 * moment, let classd_gclk be the only consumer of the audio_pll clock.
+	 */
+
+	if (gck->id != GCK_ID_CLASSD)
+		goto end;
+
+	parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
+	if (!parent)
+		goto end;
+
+	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
+		req_parent.rate = req->rate * div;
+		__clk_determine_rate(parent, &req_parent);
+		clk_generated_best_diff(req, parent, req_parent.rate, div,
+					&best_diff, &best_rate);
 
 		if (!best_diff)
 			break;
 	}
 
+end:
 	pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
 		 __func__, best_rate,
 		 __clk_get_name((req->best_parent_hw)->clk),
@@ -264,7 +292,8 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
 	init.ops = &generated_ops;
 	init.parent_names = parent_names;
 	init.num_parents = num_parents;
-	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
+	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+		CLK_SET_RATE_PARENT;
 
 	gck->id = id;
 	gck->hw.init = &init;
-- 
2.11.0

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