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| Started by | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| First post | 2017-06-20 02:10 +0200 |
| Last post | 2017-06-22 19:20 +0200 |
| Articles | 2 — 2 participants |
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[patch 54/55] x86/apic: Mark single target interrupts Thomas Gleixner <tglx@linutronix.de> - 2017-06-20 02:10 +0200
[tip:irq/core] x86/apic: Mark single target interrupts tip-bot for Thomas Gleixner <tipbot@zytor.com> - 2017-06-22 19:20 +0200
| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Date | 2017-06-20 02:10 +0200 |
| Subject | [patch 54/55] x86/apic: Mark single target interrupts |
| Message-ID | <tUeU1-1fU-3@gated-at.bofh.it> |
If the interrupt destination mode of the APIC is physical then the effective affinity is restricted to a single CPU. Mark the interrupt accordingly in the domain allocation code, so the core code can avoid pointless affinity setting attempts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/kernel/apic/vector.c | 7 +++++++ 1 file changed, 7 insertions(+) --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -371,6 +371,13 @@ static int x86_vector_alloc_irqs(struct irq_data); if (err) goto error; + /* + * If the apic destination mode is physical, then the + * effective affinity is restricted to a single target + * CPU. Mark the interrupt accordingly. + */ + if (!apic->irq_dest_mode) + irqd_set_single_target(irq_data); } return 0;
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| From | tip-bot for Thomas Gleixner <tipbot@zytor.com> |
|---|---|
| Date | 2017-06-22 19:20 +0200 |
| Subject | [tip:irq/core] x86/apic: Mark single target interrupts |
| Message-ID | <tVdVU-7HO-17@gated-at.bofh.it> |
| In reply to | #1670058 |
Commit-ID: 3ca57222c36ba31b80aa25de313f3c8ab26a8102 Gitweb: http://git.kernel.org/tip/3ca57222c36ba31b80aa25de313f3c8ab26a8102 Author: Thomas Gleixner <tglx@linutronix.de> AuthorDate: Tue, 20 Jun 2017 01:37:54 +0200 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Thu, 22 Jun 2017 18:21:26 +0200 x86/apic: Mark single target interrupts If the interrupt destination mode of the APIC is physical then the effective affinity is restricted to a single CPU. Mark the interrupt accordingly in the domain allocation code, so the core code can avoid pointless affinity setting attempts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jens Axboe <axboe@kernel.dk> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Keith Busch <keith.busch@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Christoph Hellwig <hch@lst.de> Link: http://lkml.kernel.org/r/20170619235447.508846202@linutronix.de --- arch/x86/kernel/apic/vector.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index b270a76..2567dc0 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -371,6 +371,13 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, irq_data); if (err) goto error; + /* + * If the apic destination mode is physical, then the + * effective affinity is restricted to a single target + * CPU. Mark the interrupt accordingly. + */ + if (!apic->irq_dest_mode) + irqd_set_single_target(irq_data); } return 0;
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