Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1673851 > unrolled thread
| Started by | Palmer Dabbelt <palmer@dabbelt.com> |
|---|---|
| First post | 2017-06-23 22:40 +0200 |
| Last post | 2017-06-24 16:20 +0200 |
| Articles | 3 — 3 participants |
Back to article view | Back to linux.kernel
[PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-23 22:40 +0200
Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> - 2017-06-23 22:50 +0200
Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Jonathan Corbet <corbet@lwn.net> - 2017-06-24 16:20 +0200
| From | Palmer Dabbelt <palmer@dabbelt.com> |
|---|---|
| Date | 2017-06-23 22:40 +0200 |
| Subject | [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst |
| Message-ID | <tVDwZ-6Sb-9@gated-at.bofh.it> |
I was reading the memory barries documentation in order to make sure the
RISC-V barries were correct, and I found a broken link to the atomic
operations documentation.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Acked-by: Will Deacon <will.deacon@arm.com>
---
Documentation/memory-barriers.txt | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 732f10ea382e..f1c9eaa45a57 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -498,11 +498,11 @@ And a couple of implicit varieties:
This means that ACQUIRE acts as a minimal "acquire" operation and
RELEASE acts as a minimal "release" operation.
-A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
-and RELEASE variants in addition to fully-ordered and relaxed (no barrier
-semantics) definitions. For compound atomics performing both a load and a
-store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
-only to the store portion of the operation.
+A subset of the atomic operations described in core-api/atomic_ops.rst have
+ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no
+barrier semantics) definitions. For compound atomics performing both a load
+and a store, ACQUIRE semantics apply only to the load and RELEASE semantics
+apply only to the store portion of the operation.
Memory barriers are only required where there's a possibility of interaction
between two CPUs or between a CPU and a device. If it can be guaranteed that
--
2.13.0
[toc] | [next] | [standalone]
| From | "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> |
|---|---|
| Date | 2017-06-23 22:50 +0200 |
| Message-ID | <tVDGG-6Vq-15@gated-at.bofh.it> |
| In reply to | #1673851 |
On Fri, Jun 23, 2017 at 01:31:39PM -0700, Palmer Dabbelt wrote: > I was reading the memory barries documentation in order to make sure the > RISC-V barries were correct, and I found a broken link to the atomic > operations documentation. > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > Acked-by: Will Deacon <will.deacon@arm.com> Good catch! Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> > --- > Documentation/memory-barriers.txt | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > index 732f10ea382e..f1c9eaa45a57 100644 > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -498,11 +498,11 @@ And a couple of implicit varieties: > This means that ACQUIRE acts as a minimal "acquire" operation and > RELEASE acts as a minimal "release" operation. > > -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE > -and RELEASE variants in addition to fully-ordered and relaxed (no barrier > -semantics) definitions. For compound atomics performing both a load and a > -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply > -only to the store portion of the operation. > +A subset of the atomic operations described in core-api/atomic_ops.rst have > +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no > +barrier semantics) definitions. For compound atomics performing both a load > +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics > +apply only to the store portion of the operation. > > Memory barriers are only required where there's a possibility of interaction > between two CPUs or between a CPU and a device. If it can be guaranteed that > -- > 2.13.0 >
[toc] | [prev] | [next] | [standalone]
| From | Jonathan Corbet <corbet@lwn.net> |
|---|---|
| Date | 2017-06-24 16:20 +0200 |
| Subject | Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst |
| Message-ID | <tVU4N-qf-13@gated-at.bofh.it> |
| In reply to | #1673863 |
On Fri, 23 Jun 2017 13:45:29 -0700 "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> wrote: > On Fri, Jun 23, 2017 at 01:31:39PM -0700, Palmer Dabbelt wrote: > > I was reading the memory barries documentation in order to make sure the > > RISC-V barries were correct, and I found a broken link to the atomic > > operations documentation. > > > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > > Acked-by: Will Deacon <will.deacon@arm.com> > > Good catch! > > Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Applied to the docs tree, thanks. jon
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web