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Re: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

Started byVinod Koul <vinod.koul@intel.com>
First post2017-06-22 15:00 +0200
Last post2017-06-22 15:00 +0200
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  Re: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values  correctly Vinod Koul <vinod.koul@intel.com> - 2017-06-22 15:00 +0200

#1672605 — Re: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

FromVinod Koul <vinod.koul@intel.com>
Date2017-06-22 15:00 +0200
SubjectRe: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly
Message-ID<tV9Si-4Ry-13@gated-at.bofh.it>
On Mon, Jun 19, 2017 at 04:40:04PM +0200, Thomas Breitung wrote:
> The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
> before a new value can be or-ed in.

Applied, thanks

-- 
~Vinod

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