Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1668981 > unrolled thread

[PATCH v11 0/3]add PCIe driver for Kirin PCIe

Started byXiaowei Song <songxiaowei@hisilicon.com>
First post2017-06-19 12:30 +0200
Last post2017-06-19 13:00 +0200
Articles 4 — 2 participants

Back to article view | Back to linux.kernel

Contents

  [PATCH v11 0/3]add PCIe driver for Kirin PCIe Xiaowei Song <songxiaowei@hisilicon.com> - 2017-06-19 12:30 +0200
    [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series Xiaowei Song <songxiaowei@hisilicon.com> - 2017-06-19 12:30 +0200
      Re: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC  series Wei Xu <xuwei5@hisilicon.com> - 2017-06-19 12:50 +0200
        Re: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC  series Wei Xu <xuwei5@hisilicon.com> - 2017-06-19 13:00 +0200

#1668981 — [PATCH v11 0/3]add PCIe driver for Kirin PCIe

FromXiaowei Song <songxiaowei@hisilicon.com>
Date2017-06-19 12:30 +0200
Subject[PATCH v11 0/3]add PCIe driver for Kirin PCIe
Message-ID<tU26t-1nN-13@gated-at.bofh.it>
Before Version Patches
======================
patch v9
http://www.spinics.net/lists/linux-pci/msg61821.html
patch V8
http://www.spinics.net/lists/linux-pci/msg61715.html
patch V7
https://www.spinics.net/lists/linux-pci/msg61664.html
patch V6
https://www.spinics.net/lists/linux-pci/msg61610.html

patch V4
https://www.spinics.net/lists/linux-pci/msg61406.html

patch V3
https://www.spinics.net/lists/linux-pci/msg61399.html

Changes between V11 and V9
========================
1. Fix the indent issues according to the review comments from Bjorn:
   (1) The value of reg is right-aligned in both dtsi file and Documentation file.
   (2) Re-indent the space of macro defination pointed out by Bjorn.
   (3) Adjust the space in 'struct kirin_pcie' defination.
   (4) Use dev replace of pdev->dev in function  kirin_pcie_get_clk and kirin_pcie_get_resource.
   (5) Aligned params with '(' in function kirin_apb_ctrl_writel and several others.
2. Fix the issues that compitable value in Documentation was different with .dtsi file.
3. For dependance during compiling, the dtsi patch is deleted, and it was merged in patch[1].
4. The indent style issues will be pull with MSI-patch in the next weeks;

patch[1]: https://www.spinics.net/lists/arm-kernel/msg588944.html

=========================
Changes between V8 and V7
=========================
1. Fix the indent issues in Documentation, dtsi file and macro defination.
2. Replace pdev->dev with dev in kirin_pcie_get_resource and 
   kirin_pcie_get_clk functions.
3. Put variables "pci" and "kirin_pcie" to be initialized at first
   in kirin_pcie_wr_own_config, kirin_pcie_read_dbi and other functions.
4. Add space before blankets in "Low power mode(L1 ".
5. Short the Makefile sentence to lower than 80 characters
   and delete reduntant words.
6. Use word 'located' instead of the wrong one 'lacated'.
7. Fix the problem of return value type.

Changes between V8 and V7
=========================
1. Replace 'reset-gpios' of 'reset-gpio' in Documentation.

Changes between V7 and V6
=========================
1. add enumeration log Based on Hikey960 Board with these patches.
2. fix issues as fellows:
   (1) delete reduntant blankets in macro defination,
   (2) add blank line in  kirin_pcie_clk_ctrl function.
   (3) Fix compitable property in DT with the SoC name,
       for example "hisilicon,kirin960-pcie".

Changes between V6 and V4
=========================
1. seperate Document from .dtsi patch.
2. fix issues according to review comments
   from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
   patch post method and so on.

Enumeration log
===============
These test logs come from patches running on Hikey960 Board
(1) Connect with Atheros Communications WIFI
	OF: PCI: host bridge /soc/kirin_pcie_rc@f4000000 ranges:
	OF: PCI:   MEM 0xf6000000..0xf7ffffff -> 0x00000000
	kirin-pcie f4000000.kirin_pcie_rc: PCI host bridge to bus 0000:00
	pci_bus 0000:00: root bus resource [bus 00-01]
	pci_bus 0000:00: root bus resource [mem 0xf6000000-0xf7ffffff] (bus address [0x00000000-0x01ffffff])
	pci 0000:00:00.0: [19e5:3660] type 01 class 0x060400
	pci 0000:00:00.0: reg 0x10: [mem 0xf6000000-0xf6ffffff]
	pci 0000:00:00.0: supports D1 D2
	pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
	pci 0000:01:00.0: [168c:002a] type 00 class 0x028000
	pci 0000:01:00.0: reg 0x10: [mem 0xf6000000-0xf600ffff 64bit]
	pci 0000:01:00.0: supports D1
	pci 0000:01:00.0: PME# supported from D0 D1 D3hot
	pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
	pci 0000:00:00.0: BAR 0: assigned [mem 0xf6000000-0xf6ffffff]
	pci 0000:00:00.0: BAR 14: assigned [mem 0xf7000000-0xf70fffff]
	pci 0000:01:00.0: BAR 0: assigned [mem 0xf7000000-0xf700ffff 64bit]
	pci 0000:00:00.0: PCI bridge to [bus 01]
	pci 0000:00:00.0:   bridge window [mem 0xf7000000-0xf70fffff]
	pcieport 0000:00:00.0: Signaling PME with IRQ 276
	pcieport 0000:00:00.0: AER enabled with IRQ 276	 


Xiaowei Song (3):
  PCI: hisi: Add DT binding for PCIe of Kirin SoC series
  PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
  ARM4: defconfig: Enable  Kirin PCIe

 .../devicetree/bindings/pci/kirin-pcie.txt         |  55 +++
 arch/arm64/configs/defconfig                       |   1 +
 drivers/pci/dwc/Kconfig                            |  10 +
 drivers/pci/dwc/Makefile                           |   1 +
 drivers/pci/dwc/pcie-kirin.c                       | 518 +++++++++++++++++++++
 5 files changed, 585 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
 create mode 100644 drivers/pci/dwc/pcie-kirin.c

-- 
2.11.GIT

[toc] | [next] | [standalone]

#1668984 — [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

FromXiaowei Song <songxiaowei@hisilicon.com>
Date2017-06-19 12:30 +0200
Subject[PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series
Message-ID<tU26u-1nN-35@gated-at.bofh.it>
In reply to#1668981
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/kirin-pcie.txt         | 55 ++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 000000000000..c2be01270ec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,55 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+  "dbi": controller configuration registers;
+  "apb": apb Ctrl register defined by Kirin;
+  "phy": apb PHY register defined by Kirin;
+  "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+	pcie@f4000000 {
+		compatible = "hisilicon,kirin960-pcie";
+		reg = <0x0 0xf4000000 0x0 0x1000>,
+		      <0x0 0xff3fe000 0x0 0x1000>,
+		      <0x0 0xf3f20000 0x0 0x40000>,
+		      <0x0 0xf4000000 0x0  0x2000>;
+		reg-names = "dbi","apb","phy", "config";
+		bus-range = <0x0  0x1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x02000000 0x0 0x0
+			  0x0 0xf5000000
+			  0x0 0x2000000>;
+		num-lanes = <1>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <0x0 0 0 1 &gic 0 282 4>,
+				<0x0 0 0 2 &gic 0 283 4>,
+				<0x0 0 0 3 &gic 0 284 4>,
+				<0x0 0 0 4 &gic 0 285 4>;
+		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+		clock-names = "pcie_phy_ref", "pcie_aux",
+			      "pcie_apb_phy", "pcie_apb_sys",
+			      "pcie_aclk";
+		reset-gpios = <&gpio11 1 0>;
+	};
-- 
2.11.GIT

[toc] | [prev] | [next] | [standalone]

#1668995 — Re: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

FromWei Xu <xuwei5@hisilicon.com>
Date2017-06-19 12:50 +0200
SubjectRe: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series
Message-ID<tU2pQ-1ul-15@gated-at.bofh.it>
In reply to#1668984
Hi Xiaowei,

On 2017/6/19 11:23, Xiaowei Song wrote:

Please add some commit message.

> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

I have picked up the patch from [1] and
the pull request has been merged into ARM SoC tree.
Please do not resend the same patch.
Thanks!

[1]:https://lkml.org/lkml/2017/6/14/1055

Best Regards,
Wei

>  .../devicetree/bindings/pci/kirin-pcie.txt         | 55 ++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> new file mode 100644
> index 000000000000..c2be01270ec5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> @@ -0,0 +1,55 @@
> +HiSilicon Kirin SoCs PCIe host DT description
> +
> +Kirin PCIe host controller is based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver
> +and inherits common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties
> +- compatible:
> +	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
> +- reg-names: Must include the following entries:
> +  "dbi": controller configuration registers;
> +  "apb": apb Ctrl register defined by Kirin;
> +  "phy": apb PHY register defined by Kirin;
> +  "config": PCIe configuration space registers.
> +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
> +
> +Optional properties:
> +
> +Example based on kirin960:
> +
> +	pcie@f4000000 {
> +		compatible = "hisilicon,kirin960-pcie";
> +		reg = <0x0 0xf4000000 0x0 0x1000>,
> +		      <0x0 0xff3fe000 0x0 0x1000>,
> +		      <0x0 0xf3f20000 0x0 0x40000>,
> +		      <0x0 0xf4000000 0x0  0x2000>;
> +		reg-names = "dbi","apb","phy", "config";
> +		bus-range = <0x0  0x1>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		device_type = "pci";
> +		ranges = <0x02000000 0x0 0x0
> +			  0x0 0xf5000000
> +			  0x0 0x2000000>;
> +		num-lanes = <1>;
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0xf800 0 0 7>;
> +		interrupt-map = <0x0 0 0 1 &gic 0 282 4>,
> +				<0x0 0 0 2 &gic 0 283 4>,
> +				<0x0 0 0 3 &gic 0 284 4>,
> +				<0x0 0 0 4 &gic 0 285 4>;
> +		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> +			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> +			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> +		clock-names = "pcie_phy_ref", "pcie_aux",
> +			      "pcie_apb_phy", "pcie_apb_sys",
> +			      "pcie_aclk";
> +		reset-gpios = <&gpio11 1 0>;
> +	};
>

[toc] | [prev] | [next] | [standalone]

#1669000 — Re: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

FromWei Xu <xuwei5@hisilicon.com>
Date2017-06-19 13:00 +0200
SubjectRe: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series
Message-ID<tU2zv-1xF-9@gated-at.bofh.it>
In reply to#1668995
Hi Xiaowei,

On 2017/6/19 11:44, Wei Xu wrote:
> Hi Xiaowei,
> 
> On 2017/6/19 11:23, Xiaowei Song wrote:
> 
> Please add some commit message.
> 
>> Cc: Guodong Xu <guodong.xu@linaro.org>
>> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> ---
> 
> I have picked up the patch from [1] and
> the pull request has been merged into ARM SoC tree.
> Please do not resend the same patch.
> Thanks!
> 
> [1]:https://lkml.org/lkml/2017/6/14/1055

Sorry, the above link is wrong.
It should be https://lkml.org/lkml/2017/6/14/1056

BR,
Wei

> 
> Best Regards,
> Wei
> 
>>  .../devicetree/bindings/pci/kirin-pcie.txt         | 55 ++++++++++++++++++++++
>>  1 file changed, 55 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
>> new file mode 100644
>> index 000000000000..c2be01270ec5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
>> @@ -0,0 +1,55 @@
>> +HiSilicon Kirin SoCs PCIe host DT description
>> +
>> +Kirin PCIe host controller is based on Designware PCI core.
>> +It shares common functions with PCIe Designware core driver
>> +and inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties
>> +- compatible:
>> +	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
>> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
>> +- reg-names: Must include the following entries:
>> +  "dbi": controller configuration registers;
>> +  "apb": apb Ctrl register defined by Kirin;
>> +  "phy": apb PHY register defined by Kirin;
>> +  "config": PCIe configuration space registers.
>> +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
>> +
>> +Optional properties:
>> +
>> +Example based on kirin960:
>> +
>> +	pcie@f4000000 {
>> +		compatible = "hisilicon,kirin960-pcie";
>> +		reg = <0x0 0xf4000000 0x0 0x1000>,
>> +		      <0x0 0xff3fe000 0x0 0x1000>,
>> +		      <0x0 0xf3f20000 0x0 0x40000>,
>> +		      <0x0 0xf4000000 0x0  0x2000>;
>> +		reg-names = "dbi","apb","phy", "config";
>> +		bus-range = <0x0  0x1>;
>> +		#address-cells = <3>;
>> +		#size-cells = <2>;
>> +		device_type = "pci";
>> +		ranges = <0x02000000 0x0 0x0
>> +			  0x0 0xf5000000
>> +			  0x0 0x2000000>;
>> +		num-lanes = <1>;
>> +		#interrupt-cells = <1>;
>> +		interrupt-map-mask = <0xf800 0 0 7>;
>> +		interrupt-map = <0x0 0 0 1 &gic 0 282 4>,
>> +				<0x0 0 0 2 &gic 0 283 4>,
>> +				<0x0 0 0 3 &gic 0 284 4>,
>> +				<0x0 0 0 4 &gic 0 285 4>;
>> +		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
>> +			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
>> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
>> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
>> +			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
>> +		clock-names = "pcie_phy_ref", "pcie_aux",
>> +			      "pcie_apb_phy", "pcie_apb_sys",
>> +			      "pcie_aclk";
>> +		reset-gpios = <&gpio11 1 0>;
>> +	};
>>

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web