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Groups > linux.kernel > #1666560 > unrolled thread
| Started by | Noam Camus <noamca@mellanox.com> |
|---|---|
| First post | 2017-06-15 10:50 +0200 |
| Last post | 2017-06-15 10:50 +0200 |
| Articles | 1 — 1 participant |
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[PATCH v3 11/11] ARC: [plat-eznps] avoid toggling of DPC register Noam Camus <noamca@mellanox.com> - 2017-06-15 10:50 +0200
| From | Noam Camus <noamca@mellanox.com> |
|---|---|
| Date | 2017-06-15 10:50 +0200 |
| Subject | [PATCH v3 11/11] ARC: [plat-eznps] avoid toggling of DPC register |
| Message-ID | <tSyDv-cv-1@gated-at.bofh.it> |
From: Elad Kanfi <eladkan@mellanox.com> HW bug description: in case of HW thread context switch the dpc configuration of the exiting thread is dragged one cycle into the next thread. In order to avoid the consequences of this bug, the DPC register is set to an initial value, and not changed afterwards. Signed-off-by: Elad Kanfi <eladkan@mellanox.com> Signed-off-by: Noam Camus <noamca@mellanox.com> --- arch/arc/plat-eznps/include/plat/ctop.h | 1 + arch/arc/plat-eznps/mtm.c | 12 ++++++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 7729d3d..0c7d110 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -39,6 +39,7 @@ #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018) #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020) #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024) +#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C) #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030) #define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080) #define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088) diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c index 9c78ad6..909bbd4 100644 --- a/arch/arc/plat-eznps/mtm.c +++ b/arch/arc/plat-eznps/mtm.c @@ -110,6 +110,18 @@ void mtm_enable_core(unsigned int cpu) int i; struct nps_host_reg_aux_mt_ctrl mt_ctrl; struct nps_host_reg_mtm_cfg mtm_cfg; + struct nps_host_reg_aux_dpc dpc; + + /* + * Initializing dpc register in each CPU. + * Overwriting the init value of the DPC + * register so that CMEM and FMT virtual address + * spaces are accessible, and Data Plane HW + * facilities are enabled. + */ + dpc.ien = 1; + dpc.men = 1; + write_aux_reg(CTOP_AUX_DPC, dpc.value); if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) return; -- 1.7.1
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