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Groups > linux.kernel > #1663565 > unrolled thread
| Started by | Suzuki K Poulose <suzuki.poulose@arm.com> |
|---|---|
| First post | 2017-06-12 16:40 +0200 |
| Last post | 2017-06-15 12:30 +0200 |
| Articles | 4 on this page of 24 — 4 participants |
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[PATCH 00/12] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
[PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 04/12] coresight: Add support for reading 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-13 19:50 +0200
Re: [PATCH 04/12] coresight: Add support for reading 64bit registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-13 20:00 +0200
[PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 19:50 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:20 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mike Leach <mike.leach@linaro.org> - 2017-06-15 15:40 +0200
Re: [PATCH 05/12] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:30 +0200
[PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
Re: [PATCH 06/12] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:20 +0200
[PATCH 02/12] arm64: dts: juno: Use the new coresight replicator string Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
[PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 09/12] coresight tmc: Add capability information Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:30 +0200
Re: [PATCH 09/12] coresight tmc: Add capability information Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:40 +0200
Re: [PATCH 09/12] coresight tmc: Add capability information Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:40 +0200
[PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:40 +0200
Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:30 +0200
Re: [PATCH 08/12] coresight tmc: Handle configuration types properly Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-15 16:40 +0200
[PATCH 07/12] coresight replicator: Expose replicator management registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-06-12 16:50 +0200
Re: [PATCH 07/12] coresight replicator: Expose replicator management registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-06-14 20:00 +0200
Re: [PATCH 07/12] coresight replicator: Expose replicator management registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-06-15 12:30 +0200
Page 2 of 2 — ← Prev page 1 [2]
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2017-06-15 16:40 +0200 |
| Subject | Re: [PATCH 08/12] coresight tmc: Handle configuration types properly |
| Message-ID | <tSE6e-3E5-19@gated-at.bofh.it> |
| In reply to | #1666625 |
On 15 June 2017 at 04:25, Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
> On 14/06/17 18:59, Mathieu Poirier wrote:
>>
>> On Mon, Jun 12, 2017 at 03:36:47PM +0100, Suzuki K Poulose wrote:
>>>
>>> Coresight SoC 600 defines a new configuration for TMC, Embedded Trace
>>> Streamer (ETS), indicated by 0x3 in MODE:CONFIG_TYPE. Make sure
>>> the driver handles the new type properly.
>>
>>
>> From what I see below this patch only improves readability by moving the
>> if/else
>> compound to a case statement - there is no trace of the new ETS block.
>> Readability enhancement are good but the changelog must match the code.
>
>
> Mathieu,
>
> Not really. It fixes an issue with the current code. We check for ETB and
> ETR,
> if it doesn't match either of those, we assume it is ETF which is fine with
> SoC-400.
> But with SoC-600, we could have an ETS with id 0x3 and the driver could
> treat it
> as an ETF and go on with the initialisation. This patch makes sure that we
> do check for the ETF and report that ETS is not a supported configuration.
That is the description that should go in the changelog - it reflects
exactly what this patch is doing.
Mathieu.
>
> Suzuki
>
>>
>>>
>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> ---
>>> drivers/hwtracing/coresight/coresight-tmc.c | 14 +++++++++++---
>>> 1 file changed, 11 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c
>>> b/drivers/hwtracing/coresight/coresight-tmc.c
>>> index fd5a2e0..7152656 100644
>>> --- a/drivers/hwtracing/coresight/coresight-tmc.c
>>> +++ b/drivers/hwtracing/coresight/coresight-tmc.c
>>> @@ -358,11 +358,13 @@ static int tmc_probe(struct amba_device *adev,
>>> const struct amba_id *id)
>>> desc.dev = dev;
>>> desc.groups = coresight_tmc_groups;
>>>
>>> - if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
>>> + switch (drvdata->config_type) {
>>> + case TMC_CONFIG_TYPE_ETB:
>>> desc.type = CORESIGHT_DEV_TYPE_SINK;
>>> desc.subtype.sink_subtype =
>>> CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>>> desc.ops = &tmc_etb_cs_ops;
>>> - } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
>>> + break;
>>> + case TMC_CONFIG_TYPE_ETR:
>>> desc.type = CORESIGHT_DEV_TYPE_SINK;
>>> desc.subtype.sink_subtype =
>>> CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
>>> desc.ops = &tmc_etr_cs_ops;
>>> @@ -373,10 +375,16 @@ static int tmc_probe(struct amba_device *adev,
>>> const struct amba_id *id)
>>> ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
>>> if (ret)
>>> goto out;
>>> - } else {
>>> + break;
>>> + case TMC_CONFIG_TYPE_ETF:
>>> desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
>>> desc.subtype.link_subtype =
>>> CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
>>> desc.ops = &tmc_etf_cs_ops;
>>> + break;
>>> + default:
>>> + pr_err("%s: Unsupported TMC config\n", pdata->name);
>>> + ret = -EINVAL;
>>> + goto out;
>>> }
>>>
>>> drvdata->csdev = coresight_register(&desc);
>>> --
>>> 2.7.4
>>>
>
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| From | Suzuki K Poulose <suzuki.poulose@arm.com> |
|---|---|
| Date | 2017-06-12 16:50 +0200 |
| Subject | [PATCH 07/12] coresight replicator: Expose replicator management registers |
| Message-ID | <tRyPf-3kj-11@gated-at.bofh.it> |
| In reply to | #1663565 |
Expose the idfilter* registers of the programmable replicator.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
.../hwtracing/coresight/coresight-replicator-qcom.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
index b029a5f..4dd18e0 100644
--- a/drivers/hwtracing/coresight/coresight-replicator-qcom.c
+++ b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
@@ -95,6 +95,26 @@ static const struct coresight_ops replicator_cs_ops = {
.link_ops = &replicator_link_ops,
};
+coresight_simple_func(struct replicator_state, NULL, idfilter0,
+ REPLICATOR_IDFILTER0);
+coresight_simple_func(struct replicator_state, NULL, idfilter1,
+ REPLICATOR_IDFILTER1);
+static struct attribute *replicator_mgmt_attrs[] = {
+ &dev_attr_idfilter0.attr,
+ &dev_attr_idfilter1.attr,
+ NULL,
+};
+
+static const struct attribute_group replicator_mgmt_group = {
+ .attrs = replicator_mgmt_attrs,
+ .name = "mgmt",
+};
+
+static const struct attribute_group *replicator_groups[] = {
+ &replicator_mgmt_group,
+ NULL,
+};
+
static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
{
int ret;
@@ -139,6 +159,7 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
desc.ops = &replicator_cs_ops;
desc.pdata = adev->dev.platform_data;
desc.dev = &adev->dev;
+ desc.groups = replicator_groups;
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
--
2.7.4
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| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Date | 2017-06-14 20:00 +0200 |
| Subject | Re: [PATCH 07/12] coresight replicator: Expose replicator management registers |
| Message-ID | <tSkKd-8fL-3@gated-at.bofh.it> |
| In reply to | #1663582 |
On Mon, Jun 12, 2017 at 03:36:46PM +0100, Suzuki K Poulose wrote:
> Expose the idfilter* registers of the programmable replicator.
Is this for SoC600 only? If so we need to make sure these are not visible when
operating an SoC400 replicator. Otherwise simply disregard my statement.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> .../hwtracing/coresight/coresight-replicator-qcom.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-replicator-qcom.c b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
> index b029a5f..4dd18e0 100644
> --- a/drivers/hwtracing/coresight/coresight-replicator-qcom.c
> +++ b/drivers/hwtracing/coresight/coresight-replicator-qcom.c
> @@ -95,6 +95,26 @@ static const struct coresight_ops replicator_cs_ops = {
> .link_ops = &replicator_link_ops,
> };
>
> +coresight_simple_func(struct replicator_state, NULL, idfilter0,
> + REPLICATOR_IDFILTER0);
> +coresight_simple_func(struct replicator_state, NULL, idfilter1,
> + REPLICATOR_IDFILTER1);
> +static struct attribute *replicator_mgmt_attrs[] = {
> + &dev_attr_idfilter0.attr,
> + &dev_attr_idfilter1.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group replicator_mgmt_group = {
> + .attrs = replicator_mgmt_attrs,
> + .name = "mgmt",
> +};
> +
> +static const struct attribute_group *replicator_groups[] = {
> + &replicator_mgmt_group,
> + NULL,
> +};
> +
> static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
> {
> int ret;
> @@ -139,6 +159,7 @@ static int replicator_probe(struct amba_device *adev, const struct amba_id *id)
> desc.ops = &replicator_cs_ops;
> desc.pdata = adev->dev.platform_data;
> desc.dev = &adev->dev;
> + desc.groups = replicator_groups;
> drvdata->csdev = coresight_register(&desc);
> if (IS_ERR(drvdata->csdev))
> return PTR_ERR(drvdata->csdev);
> --
> 2.7.4
>
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| From | Suzuki K Poulose <Suzuki.Poulose@arm.com> |
|---|---|
| Date | 2017-06-15 12:30 +0200 |
| Subject | Re: [PATCH 07/12] coresight replicator: Expose replicator management registers |
| Message-ID | <tSAci-1ga-9@gated-at.bofh.it> |
| In reply to | #1666116 |
On 14/06/17 18:54, Mathieu Poirier wrote: > On Mon, Jun 12, 2017 at 03:36:46PM +0100, Suzuki K Poulose wrote: >> Expose the idfilter* registers of the programmable replicator. > > Is this for SoC600 only? If so we need to make sure these are not visible when > operating an SoC400 replicator. Otherwise simply disregard my statement. No, this is for the existing dynamic replicator, which is also compatible with the one in SoC-600. In the future, we may be able to support multiple trace sessions (i.e, distinct source-sink pairs using a shared dynamic replicator to filter the data based on the trace-id). Right now we simple switch off the other side of the replicator, when we enable the port connected to the sink. I found these useful while debugging trace generation issue on one of the platforms. Suzuki
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