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| Started by | Borislav Petkov <bp@alien8.de> |
|---|---|
| First post | 2017-06-13 18:30 +0200 |
| Last post | 2017-06-14 11:30 +0200 |
| Articles | 2 — 2 participants |
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[PATCH 7/8] x86/mce: Don't disable MCA banks when offlining a CPU on AMD Borislav Petkov <bp@alien8.de> - 2017-06-13 18:30 +0200
[tip:ras/core] x86/mce: Don't disable MCA banks when offlining a CPU on AMD tip-bot for Yazen Ghannam <tipbot@zytor.com> - 2017-06-14 11:30 +0200
| From | Borislav Petkov <bp@alien8.de> |
|---|---|
| Date | 2017-06-13 18:30 +0200 |
| Subject | [PATCH 7/8] x86/mce: Don't disable MCA banks when offlining a CPU on AMD |
| Message-ID | <tRWRA-1MW-9@gated-at.bofh.it> |
From: Yazen Ghannam <yazen.ghannam@amd.com>
AMD systems have non-core, shared MCA banks within a die. These banks
are controlled by a master CPU per die. If this CPU is offlined then all
the shared banks are disabled in addition to the CPU's core banks.
Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
between SMT thread siblings. If a CPU is offlined then all its sibling's
MCA banks are also disabled.
Extend the existing vendor check to AMD too.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1496692427-7991-1-git-send-email-Yazen.Ghannam@amd.com
[ Fixup comment. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 5cfbaeb6529a..3c54c2b9efc2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1912,12 +1912,13 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
- * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
+ * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
return;
mce_disable_error_reporting();
--
2.13.0
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| From | tip-bot for Yazen Ghannam <tipbot@zytor.com> |
|---|---|
| Date | 2017-06-14 11:30 +0200 |
| Subject | [tip:ras/core] x86/mce: Don't disable MCA banks when offlining a CPU on AMD |
| Message-ID | <tScMH-3nJ-29@gated-at.bofh.it> |
| In reply to | #1664992 |
Commit-ID: ec33838244c8535b23b8d24b167996fd1318bb68
Gitweb: http://git.kernel.org/tip/ec33838244c8535b23b8d24b167996fd1318bb68
Author: Yazen Ghannam <yazen.ghannam@amd.com>
AuthorDate: Tue, 13 Jun 2017 18:28:34 +0200
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 14 Jun 2017 07:32:09 +0200
x86/mce: Don't disable MCA banks when offlining a CPU on AMD
AMD systems have non-core, shared MCA banks within a die. These banks
are controlled by a master CPU per die. If this CPU is offlined then all
the shared banks are disabled in addition to the CPU's core banks.
Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
between SMT thread siblings. If a CPU is offlined then all its sibling's
MCA banks are also disabled.
Extend the existing vendor check to AMD too.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
[ Fix up comment. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170613162835.30750-8-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 5cfbaeb..3c54c2b 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1912,12 +1912,13 @@ static void mce_disable_error_reporting(void)
static void vendor_disable_error_reporting(void)
{
/*
- * Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
+ * Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
* Disabling them for just a single offlined CPU is bad, since it will
* inhibit reporting for all shared resources on the socket like the
* last level cache (LLC), the integrated memory controller (iMC), etc.
*/
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
return;
mce_disable_error_reporting();
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