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Groups > linux.kernel > #1653892 > unrolled thread
| Started by | Xiaowei Song <songxiaowei@hisilicon.com> |
|---|---|
| First post | 2017-05-31 09:10 +0200 |
| Last post | 2017-05-31 19:10 +0200 |
| Articles | 9 — 5 participants |
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[PATCH v9 0/4] add PCIe driver for Kirin PCIe Xiaowei Song <songxiaowei@hisilicon.com> - 2017-05-31 09:10 +0200
[PATCH v9 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series Xiaowei Song <songxiaowei@hisilicon.com> - 2017-05-31 09:10 +0200
[PATCH v9 4/4] ARM64: defconfig: Enable Kirin PCIe Xiaowei Song <songxiaowei@hisilicon.com> - 2017-05-31 09:10 +0200
[PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node Xiaowei Song <songxiaowei@hisilicon.com> - 2017-05-31 09:10 +0200
Re: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node kbuild test robot <lkp@intel.com> - 2017-06-04 02:10 +0200
Re: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node Arnd Bergmann <arnd@arndb.de> - 2017-06-06 11:30 +0200
Re: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node Guodong Xu <guodong.xu@linaro.org> - 2017-06-06 13:30 +0200
[PATCH v9 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC Xiaowei Song <songxiaowei@hisilicon.com> - 2017-05-31 09:10 +0200
Re: [PATCH v9 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC "Jingoo Han" <jingoohan1@gmail.com> - 2017-05-31 19:10 +0200
| From | Xiaowei Song <songxiaowei@hisilicon.com> |
|---|---|
| Date | 2017-05-31 09:10 +0200 |
| Subject | [PATCH v9 0/4] add PCIe driver for Kirin PCIe |
| Message-ID | <tN5Vv-1DA-3@gated-at.bofh.it> |
Before Version Patches
======================
patch V8
http://www.spinics.net/lists/linux-pci/msg61715.html
patch V7
https://www.spinics.net/lists/linux-pci/msg61664.html
patch V6
https://www.spinics.net/lists/linux-pci/msg61610.html
patch V4
https://www.spinics.net/lists/linux-pci/msg61406.html
patch V3
https://www.spinics.net/lists/linux-pci/msg61399.html
Changes between V8 and V7
=========================
1. Fix the indent issues in Documentation, dtsi file and macro defination.
2. Replace pdev->dev with dev in kirin_pcie_get_resource and
kirin_pcie_get_clk functions.
3. Put variables "pci" and "kirin_pcie" to be initialized at first
in kirin_pcie_wr_own_config, kirin_pcie_read_dbi and other functions.
4. Add space before blankets in "Low power mode(L1 ".
5. Short the Makefile sentence to lower than 80 characters
and delete reduntant words.
6. Use word 'located' instead of the wrong one 'lacated'.
7. Fix the problem of return value type.
Changes between V8 and V7
=========================
1. Replace 'reset-gpios' of 'reset-gpio' in Documentation.
Changes between V7 and V6
=========================
1. add enumeration log Based on Hikey960 Board with these patches.
2. fix issues as fellows:
(1) delete reduntant blankets in macro defination,
(2) add blank line in kirin_pcie_clk_ctrl function.
(3) Fix compitable property in DT with the SoC name,
for example "hisilicon,kirin960-pcie".
Changes between V6 and V4
=========================
1. seperate Document from .dtsi patch.
2. fix issues according to review comments
from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
patch post method and so on.
Enumeration log
===============
These test logs come from patches running on Hikey960 Board
(1) Connect with Atheros Communications WIFI
OF: PCI: host bridge /soc/kirin_pcie_rc@f4000000 ranges:
OF: PCI: MEM 0xf6000000..0xf7ffffff -> 0x00000000
kirin-pcie f4000000.kirin_pcie_rc: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [bus 00-01]
pci_bus 0000:00: root bus resource [mem 0xf6000000-0xf7ffffff] (bus address [0x00000000-0x01ffffff])
pci 0000:00:00.0: [19e5:3660] type 01 class 0x060400
pci 0000:00:00.0: reg 0x10: [mem 0xf6000000-0xf6ffffff]
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
pci 0000:01:00.0: [168c:002a] type 00 class 0x028000
pci 0000:01:00.0: reg 0x10: [mem 0xf6000000-0xf600ffff 64bit]
pci 0000:01:00.0: supports D1
pci 0000:01:00.0: PME# supported from D0 D1 D3hot
pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
pci 0000:00:00.0: BAR 0: assigned [mem 0xf6000000-0xf6ffffff]
pci 0000:00:00.0: BAR 14: assigned [mem 0xf7000000-0xf70fffff]
pci 0000:01:00.0: BAR 0: assigned [mem 0xf7000000-0xf700ffff 64bit]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [mem 0xf7000000-0xf70fffff]
pcieport 0000:00:00.0: Signaling PME with IRQ 276
pcieport 0000:00:00.0: AER enabled with IRQ 276
(2) Connect with Sandisk SSD
OF: PCI: host bridge /soc/kirin_pcie_rc@f4000000 ranges:
OF: PCI: MEM 0xf6000000..0xf7ffffff -> 0x00000000
kirin-pcie f4000000.kirin_pcie_rc: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [bus 00-01]
pci_bus 0000:00: root bus resource [mem 0xf6000000-0xf7ffffff] (bus address [0x00000000-0x01ffffff])
pci 0000:00:00.0: [19e5:3660] type 01 class 0x060400
pci 0000:00:00.0: reg 0x10: [mem 0xf6000000-0xf6ffffff]
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
pci 0000:01:00.0: [1b4b:1093] type 00 class 0x010802
pci 0000:01:00.0: reg 0x10: [mem 0xf6000000-0xf6003fff 64bit]
pci 0000:01:00.0: reg 0x30: [mem 0xf6000000-0xf600ffff pref]
pci 0000:00:00.0: BAR 0: assigned [mem 0xf6000000-0xf6ffffff]
pci 0000:00:00.0: BAR 14: assigned [mem 0xf7000000-0xf70fffff]
pci 0000:00:00.0: BAR 15: assigned [mem 0xf7100000-0xf71fffff pref]
pci 0000:01:00.0: BAR 6: assigned [mem 0xf7100000-0xf710ffff pref]
pci 0000:01:00.0: BAR 0: assigned [mem 0xf7000000-0xf7003fff 64bit]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [mem 0xf7000000-0xf70fffff]
pci 0000:00:00.0: bridge window [mem 0xf7100000-0xf71fffff pref]
pcieport 0000:00:00.0: Signaling PME with IRQ 276
pcieport 0000:00:00.0: AER enabled with IRQ 276
Patches list
============
Xiaowei Song (4):
PCI: hisi: Add DT binding for PCIe of Kirin SoC series
arm64: dts: hisi: add kirin pcie node
PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
ARM64: defconfig: Enable Kirin PCIe
.../devicetree/bindings/pci/kirin-pcie.txt | 50 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 ++
arch/arm64/configs/defconfig | 1 +
drivers/pci/dwc/Kconfig | 10 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-kirin.c | 514 +++++++++++++++++++++
6 files changed, 607 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
create mode 100644 drivers/pci/dwc/pcie-kirin.c
--
2.11.GIT
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| From | Xiaowei Song <songxiaowei@hisilicon.com> |
|---|---|
| Date | 2017-05-31 09:10 +0200 |
| Subject | [PATCH v9 1/4] PCI: hisi: Add DT binding for PCIe of Kirin SoC series |
| Message-ID | <tN5Vw-1DA-15@gated-at.bofh.it> |
| In reply to | #1653892 |
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 000000000000..68ffa0fbcd73
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,50 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+ "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register defined by Kirin;
+ "phy": apb PHY register defined by Kirin;
+ "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
--
2.11.GIT
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| From | Xiaowei Song <songxiaowei@hisilicon.com> |
|---|---|
| Date | 2017-05-31 09:10 +0200 |
| Subject | [PATCH v9 4/4] ARM64: defconfig: Enable Kirin PCIe |
| Message-ID | <tN5Vw-1DA-35@gated-at.bofh.it> |
| In reply to | #1653892 |
Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7c48028ec64a..d56d8f1062ab 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -71,6 +71,7 @@ CONFIG_PCI_XGENE=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y +CONFIG_PCIE_KIRIN=y CONFIG_PCIE_ARMADA_8K=y CONFIG_ARM64_VA_BITS_48=y CONFIG_SCHED_MC=y -- 2.11.GIT
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| From | Xiaowei Song <songxiaowei@hisilicon.com> |
|---|---|
| Date | 2017-05-31 09:10 +0200 |
| Subject | [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node |
| Message-ID | <tN5Vx-1DA-39@gated-at.bofh.it> |
| In reply to | #1653892 |
Add PCIe node for hi3660, and add binding documentation.
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..e8feb2fb4d53 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xF5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0
+ 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ status = "ok";
+ };
};
};
--
2.11.GIT
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| From | kbuild test robot <lkp@intel.com> |
|---|---|
| Date | 2017-06-04 02:10 +0200 |
| Subject | Re: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node |
| Message-ID | <tOrhf-5v6-11@gated-at.bofh.it> |
| In reply to | #1653898 |
[Multipart message — attachments visible in raw view] — view raw
Hi Xiaowei,
[auto build test ERROR on pci/next]
[also build test ERROR on v4.12-rc3 next-20170602]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Xiaowei-Song/add-PCIe-driver-for-Kirin-PCIe/20170531-182118
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-allnoconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
>> FATAL ERROR: Unable to parse input tree
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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| From | Arnd Bergmann <arnd@arndb.de> |
|---|---|
| Date | 2017-06-06 11:30 +0200 |
| Subject | Re: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node |
| Message-ID | <tPiYh-6PD-1@gated-at.bofh.it> |
| In reply to | #1656964 |
On Sun, Jun 4, 2017 at 2:03 AM, kbuild test robot <lkp@intel.com> wrote:
> Hi Xiaowei,
>
> [auto build test ERROR on pci/next]
> [also build test ERROR on v4.12-rc3 next-20170602]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Xiaowei-Song/add-PCIe-driver-for-Kirin-PCIe/20170531-182118
> base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
> config: arm64-allnoconfig (attached as .config)
> compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
> wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm64
>
> All errors (new ones prefixed by >>):
>
>>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
>>> FATAL ERROR: Unable to parse input tree
We keep getting the build errors for patch submissions. Obviously the patch is
still broken and can't be merged as-is. What is the plan for merging the series?
The other patches all seem fine IIRC.
Arnd
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| From | Guodong Xu <guodong.xu@linaro.org> |
|---|---|
| Date | 2017-06-06 13:30 +0200 |
| Subject | Re: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node |
| Message-ID | <tPkQp-89v-15@gated-at.bofh.it> |
| In reply to | #1658521 |
Hi, Arnd On Tue, Jun 6, 2017 at 5:23 PM, Arnd Bergmann <arnd@arndb.de> wrote: > On Sun, Jun 4, 2017 at 2:03 AM, kbuild test robot <lkp@intel.com> wrote: >> Hi Xiaowei, >> >> [auto build test ERROR on pci/next] >> [also build test ERROR on v4.12-rc3 next-20170602] >> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] >> >> url: https://github.com/0day-ci/linux/commits/Xiaowei-Song/add-PCIe-driver-for-Kirin-PCIe/20170531-182118 >> base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next >> config: arm64-allnoconfig (attached as .config) >> compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705 >> reproduce: >> wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross >> chmod +x ~/bin/make.cross >> # save the attached .config to linux build tree >> make.cross ARCH=arm64 >> >> All errors (new ones prefixed by >>): >> >>>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error >>>> FATAL ERROR: Unable to parse input tree > > We keep getting the build errors for patch submissions. Obviously the patch is > still broken and can't be merged as-is. What is the plan for merging the series? > This dts patch can be applied to dts series [1]. For upstream review purpose, hi3660-hikey960 dts patches, which don't have a related driver changes, are sent in [1]. Other patches, which need driver changes, like this one, are sent together with driver. Patchset [1] is now at its v2 review. Rob Herring already gave his ACK for some of them in v1. Hopefully I can get more ACK for remaining ones, and make them ready for v4.13 merging window. [1], http://www.spinics.net/lists/devicetree/msg178303.html -Guodong > The other patches all seem fine IIRC. > > Arnd
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| From | Xiaowei Song <songxiaowei@hisilicon.com> |
|---|---|
| Date | 2017-05-31 09:10 +0200 |
| Subject | [PATCH v9 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC |
| Message-ID | <tN5Vw-1DA-25@gated-at.bofh.it> |
| In reply to | #1653892 |
Hisilicon PCIe Driver shares the common functions for PCIe dw-host
The poweron functions is developed on hi3660 SoC,
while Others Functions are common for Kirin series SoCs.
Low power mode (L1 sub-state and Suspend/Resume), hotplug
and MSI feature are not supported currently.
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
drivers/pci/dwc/Kconfig | 10 +
drivers/pci/dwc/Makefile | 1 +
drivers/pci/dwc/pcie-kirin.c | 514 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 525 insertions(+)
create mode 100644 drivers/pci/dwc/pcie-kirin.c
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index d2d2ba5b8a68..afecfb2b6ff4 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -130,4 +130,14 @@ config PCIE_ARTPEC6
Say Y here to enable PCIe controller support on Axis ARTPEC-6
SoCs. This PCIe controller uses the DesignWare core.
+config PCIE_KIRIN
+ depends on OF && ARM64
+ bool "HiSilicon Kirin series SoCs PCIe controllers"
+ depends on PCI
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support
+ on HiSilicon Kirin series SoCs.
+
endmenu
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c28798..4bd69bacd4ab 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
+obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
new file mode 100644
index 000000000000..f63e6548efae
--- /dev/null
+++ b/drivers/pci/dwc/pcie-kirin.c
@@ -0,0 +1,514 @@
+/*
+ * PCIe host controller driver for Kirin Phone SoCs
+ *
+ * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
+ * http://www.huawei.com
+ *
+ * Author: Xiaowei Song <songxiaowei@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/compiler.h>
+#include <linux/compiler.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include "pcie-designware.h"
+
+#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
+
+#define REF_CLK_FREQ 100000000
+
+/* PCIe ELBI registers */
+#define SOC_PCIECTRL_CTRL0_ADDR 0x000
+#define SOC_PCIECTRL_CTRL1_ADDR 0x004
+#define SOC_PCIEPHY_CTRL2_ADDR 0x008
+#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
+#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
+
+/* info located in APB */
+#define PCIE_APP_LTSSM_ENABLE 0x01c
+#define PCIE_APB_PHY_CTRL0 0x0
+#define PCIE_APB_PHY_CTRL1 0x4
+#define PCIE_APB_PHY_STATUS0 0x400
+#define PCIE_LINKUP_ENABLE (0x8020)
+#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
+#define PIPE_CLK_STABLE (0x1 << 19)
+#define PIPE_CLK_MAX_TRY_TIMES 10
+#define PHY_REF_PAD_BIT (0x1 << 8)
+#define PHY_PWR_DOWN_BIT (0x1 << 22)
+#define PHY_RST_ACK_BIT (0x1 << 16)
+
+/* info located in sysctrl */
+#define SCTRL_PCIE_CMOS_OFFSET 0x60
+#define SCTRL_PCIE_CMOS_BIT 0x10
+#define SCTRL_PCIE_ISO_OFFSET 0x44
+#define SCTRL_PCIE_ISO_BIT 0x30
+#define SCTRL_PCIE_HPCLK_OFFSET 0x190
+#define SCTRL_PCIE_HPCLK_BIT 0x184000
+#define SCTRL_PCIE_OE_OFFSET 0x14a
+#define PCIE_DEBOUNCE_PARAM 0xF0F400
+#define PCIE_OE_BYPASS (0x3 << 28)
+
+/* peri_crg ctrl */
+#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
+#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
+
+/* Time for delay */
+#define REF_2_PERST_MIN 20000
+#define REF_2_PERST_MAX 25000
+#define PERST_2_ACCESS_MIN 10000
+#define PERST_2_ACCESS_MAX 12000
+#define LINK_WAIT_MIN 900
+#define LINK_WAIT_MAX 1000
+#define PIPE_CLK_WAIT_MIN 550
+#define PIPE_CLK_WAIT_MAX 600
+
+struct kirin_pcie {
+ struct dw_pcie *pci;
+ void __iomem *apb_base;
+ void __iomem *phy_base;
+ struct regmap *crgctrl;
+ struct regmap *sysctrl;
+ struct clk *apb_sys_clk;
+ struct clk *apb_phy_clk;
+ struct clk *phy_ref_clk;
+ struct clk *pcie_aclk;
+ struct clk *pcie_aux_clk;
+ int gpio_id_reset;
+};
+
+/* Registers in PCIeCTRL */
+static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
+ u32 val, u32 reg)
+{
+ writel(val, kirin_pcie->apb_base + reg);
+}
+
+static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
+{
+ return readl(kirin_pcie->apb_base + reg);
+}
+
+/* Registers in PCIePHY */
+static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
+ u32 val, u32 reg)
+{
+ writel(val, kirin_pcie->phy_base + reg);
+}
+
+static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg)
+{
+ return readl(kirin_pcie->phy_base + reg);
+}
+
+static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+ kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
+ if (IS_ERR(kirin_pcie->phy_ref_clk))
+ return PTR_ERR(kirin_pcie->phy_ref_clk);
+
+ kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
+ if (IS_ERR(kirin_pcie->pcie_aux_clk))
+ return PTR_ERR(kirin_pcie->pcie_aux_clk);
+
+ kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
+ if (IS_ERR(kirin_pcie->apb_phy_clk))
+ return PTR_ERR(kirin_pcie->apb_phy_clk);
+
+ kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
+ if (IS_ERR(kirin_pcie->apb_sys_clk))
+ return PTR_ERR(kirin_pcie->apb_sys_clk);
+
+ kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
+ if (IS_ERR(kirin_pcie->pcie_aclk))
+ return PTR_ERR(kirin_pcie->pcie_aclk);
+
+ return 0;
+}
+
+static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
+ struct platform_device *pdev)
+{
+ struct resource *apb;
+ struct resource *phy;
+ struct resource *dbi;
+ struct device *dev = &pdev->dev;
+
+ apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
+ kirin_pcie->apb_base = devm_ioremap_resource(dev, apb);
+ if (IS_ERR(kirin_pcie->apb_base))
+ return PTR_ERR(kirin_pcie->apb_base);
+
+ phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
+ kirin_pcie->phy_base = devm_ioremap_resource(dev, phy);
+ if (IS_ERR(kirin_pcie->phy_base))
+ return PTR_ERR(kirin_pcie->phy_base);
+
+ dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+ kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi);
+ if (IS_ERR(kirin_pcie->pci->dbi_base))
+ return PTR_ERR(kirin_pcie->pci->dbi_base);
+
+ kirin_pcie->crgctrl =
+ syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
+ if (IS_ERR(kirin_pcie->crgctrl))
+ return PTR_ERR(kirin_pcie->crgctrl);
+
+ kirin_pcie->sysctrl =
+ syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
+ if (IS_ERR(kirin_pcie->sysctrl))
+ return PTR_ERR(kirin_pcie->sysctrl);
+
+ return 0;
+}
+
+static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
+{
+ u32 reg_val;
+ u32 time = PIPE_CLK_MAX_TRY_TIMES;
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+ reg_val &= ~PHY_REF_PAD_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
+ reg_val &= ~PHY_PWR_DOWN_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
+ udelay(10);
+
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+ reg_val &= ~PHY_RST_ACK_BIT;
+ kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+ usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
+ reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+ if (reg_val & PIPE_CLK_STABLE) {
+ dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
+{
+ u32 val;
+
+ regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
+ val |= PCIE_DEBOUNCE_PARAM;
+ val &= ~PCIE_OE_BYPASS;
+ regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
+}
+
+static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
+{
+ int ret = 0;
+
+ if (!enable)
+ goto close_clk;
+
+ ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
+ if (ret)
+ goto apb_sys_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
+ if (ret)
+ goto apb_phy_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
+ if (ret)
+ goto aclk_fail;
+
+ ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
+ if (ret)
+ goto aux_clk_fail;
+
+ return 0;
+
+close_clk:
+ clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
+aux_clk_fail:
+ clk_disable_unprepare(kirin_pcie->pcie_aclk);
+aclk_fail:
+ clk_disable_unprepare(kirin_pcie->apb_phy_clk);
+apb_phy_fail:
+ clk_disable_unprepare(kirin_pcie->apb_sys_clk);
+apb_sys_fail:
+ clk_disable_unprepare(kirin_pcie->phy_ref_clk);
+
+ return ret;
+}
+
+static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
+{
+ int ret;
+
+ /* Power supply for Host */
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
+ udelay(100);
+ kirin_pcie_oe_enable(kirin_pcie);
+
+ ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
+ if (ret)
+ return ret;
+
+ /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
+ regmap_write(kirin_pcie->crgctrl,
+ CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
+ regmap_write(kirin_pcie->sysctrl,
+ SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
+
+ ret = kirin_pcie_phy_init(kirin_pcie);
+ if (ret)
+ goto close_clk;
+
+ /* perst assert Endpoint */
+ if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
+ usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
+ ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
+ if (ret)
+ goto close_clk;
+ usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
+
+ return 0;
+ }
+
+close_clk:
+ kirin_pcie_clk_ctrl(kirin_pcie, false);
+ return ret;
+}
+
+static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
+ bool on)
+{
+ u32 val;
+
+ val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
+ if (on)
+ val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+ else
+ val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+ kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
+}
+
+static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
+ bool on)
+{
+ u32 val;
+
+ val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
+ if (on)
+ val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+ else
+ val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+ kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
+}
+
+static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
+ int where, int size, u32 *val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ int ret;
+
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+ ret = dw_pcie_read(pci->dbi_base + where, size, val);
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
+ int where, int size, u32 val)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ int ret;
+
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+ ret = dw_pcie_write(pci->dbi_base + where, size, val);
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ u32 ret;
+
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+ dw_pcie_read(base + reg, size, &ret);
+ kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+ return ret;
+}
+
+static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+ u32 reg, size_t size, u32 val)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+ dw_pcie_write(base + reg, size, val);
+ kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+}
+
+static int kirin_pcie_link_up(struct dw_pcie *pci)
+{
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+
+ if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
+ return 1;
+
+ return 0;
+}
+
+static int kirin_pcie_establish_link(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+ int count = 0;
+
+ if (kirin_pcie_link_up(pci))
+ return 0;
+
+ dw_pcie_setup_rc(pp);
+
+ /* assert LTSSM enable */
+ kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
+ PCIE_APP_LTSSM_ENABLE);
+
+ /* check if the link is up or not */
+ while (!kirin_pcie_link_up(pci)) {
+ usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
+ count++;
+ if (count == 1000) {
+ dev_err(pci->dev, "Link Fail\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static void kirin_pcie_host_init(struct pcie_port *pp)
+{
+ kirin_pcie_establish_link(pp);
+}
+
+static struct dw_pcie_ops kirin_dw_pcie_ops = {
+ .read_dbi = kirin_pcie_read_dbi,
+ .write_dbi = kirin_pcie_write_dbi,
+ .link_up = kirin_pcie_link_up,
+};
+
+static struct dw_pcie_host_ops kirin_pcie_host_ops = {
+ .rd_own_conf = kirin_pcie_rd_own_conf,
+ .wr_own_conf = kirin_pcie_wr_own_conf,
+ .host_init = kirin_pcie_host_init,
+};
+
+static int __init kirin_add_pcie_port(struct dw_pcie *pci,
+ struct platform_device *pdev)
+{
+ pci->pp.ops = &kirin_pcie_host_ops;
+
+ return dw_pcie_host_init(&pci->pp);
+}
+
+static int kirin_pcie_probe(struct platform_device *pdev)
+{
+ struct kirin_pcie *kirin_pcie;
+ struct dw_pcie *pci;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ if (!dev->of_node) {
+ dev_err(&pdev->dev, "NULL node\n");
+ return -EINVAL;
+ }
+
+ kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
+ if (!kirin_pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ pci->dev = dev;
+ pci->ops = &kirin_dw_pcie_ops;
+ kirin_pcie->pci = pci;
+
+ ret = kirin_pcie_get_clk(kirin_pcie, pdev);
+ if (ret)
+ return ret;
+
+ ret = kirin_pcie_get_resource(kirin_pcie, pdev);
+ if (ret)
+ return ret;
+
+ kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
+ "reset-gpio", 0);
+ if (kirin_pcie->gpio_id_reset < 0)
+ return -ENODEV;
+
+ ret = kirin_pcie_power_on(kirin_pcie);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, kirin_pcie);
+
+ return kirin_add_pcie_port(pci, pdev);
+}
+
+static const struct of_device_id kirin_pcie_match[] = {
+ { .compatible = "hisilicon,kirin960-pcie" },
+ {},
+};
+
+struct platform_driver kirin_pcie_driver = {
+ .probe = kirin_pcie_probe,
+ .driver = {
+ .name = "kirin-pcie",
+ .of_match_table = kirin_pcie_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(kirin_pcie_driver);
--
2.11.GIT
[toc] | [prev] | [next] | [standalone]
| From | "Jingoo Han" <jingoohan1@gmail.com> |
|---|---|
| Date | 2017-05-31 19:10 +0200 |
| Subject | Re: [PATCH v9 3/4] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC |
| Message-ID | <tNfia-7EL-21@gated-at.bofh.it> |
| In reply to | #1653899 |
On Wednesday, May 31, 2017 3:01 AM, Xiaowei Song wrote:
>
> Hisilicon PCIe Driver shares the common functions for PCIe dw-host
>
> The poweron functions is developed on hi3660 SoC,
> while Others Functions are common for Kirin series SoCs.
>
> Low power mode (L1 sub-state and Suspend/Resume), hotplug
> and MSI feature are not supported currently.
>
> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> drivers/pci/dwc/Kconfig | 10 +
> drivers/pci/dwc/Makefile | 1 +
> drivers/pci/dwc/pcie-kirin.c | 514
> +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 525 insertions(+)
> create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index d2d2ba5b8a68..afecfb2b6ff4 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -130,4 +130,14 @@ config PCIE_ARTPEC6
> Say Y here to enable PCIe controller support on Axis ARTPEC-6
> SoCs. This PCIe controller uses the DesignWare core.
>
> +config PCIE_KIRIN
> + depends on OF && ARM64
> + bool "HiSilicon Kirin series SoCs PCIe controllers"
> + depends on PCI
> + select PCIEPORTBUS
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want PCIe controller support
> + on HiSilicon Kirin series SoCs.
> +
> endmenu
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c28798..4bd69bacd4ab 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
> new file mode 100644
> index 000000000000..f63e6548efae
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-kirin.c
> @@ -0,0 +1,514 @@
> +/*
> + * PCIe host controller driver for Kirin Phone SoCs
> + *
> + * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
> + * http://www.huawei.com
> + *
> + * Author: Xiaowei Song <songxiaowei@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/compiler.h>
> +#include <linux/compiler.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_regs.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include "pcie-designware.h"
> +
> +#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
> +
> +#define REF_CLK_FREQ 100000000
> +
> +/* PCIe ELBI registers */
> +#define SOC_PCIECTRL_CTRL0_ADDR 0x000
> +#define SOC_PCIECTRL_CTRL1_ADDR 0x004
> +#define SOC_PCIEPHY_CTRL2_ADDR 0x008
> +#define SOC_PCIEPHY_CTRL3_ADDR 0x00c
> +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
> +
> +/* info located in APB */
> +#define PCIE_APP_LTSSM_ENABLE 0x01c
> +#define PCIE_APB_PHY_CTRL0 0x0
> +#define PCIE_APB_PHY_CTRL1 0x4
> +#define PCIE_APB_PHY_STATUS0 0x400
> +#define PCIE_LINKUP_ENABLE (0x8020)
> +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11)
> +#define PIPE_CLK_STABLE (0x1 << 19)
> +#define PIPE_CLK_MAX_TRY_TIMES 10
> +#define PHY_REF_PAD_BIT (0x1 << 8)
> +#define PHY_PWR_DOWN_BIT (0x1 << 22)
> +#define PHY_RST_ACK_BIT (0x1 << 16)
> +
> +/* info located in sysctrl */
> +#define SCTRL_PCIE_CMOS_OFFSET 0x60
> +#define SCTRL_PCIE_CMOS_BIT 0x10
> +#define SCTRL_PCIE_ISO_OFFSET 0x44
> +#define SCTRL_PCIE_ISO_BIT 0x30
> +#define SCTRL_PCIE_HPCLK_OFFSET 0x190
> +#define SCTRL_PCIE_HPCLK_BIT 0x184000
> +#define SCTRL_PCIE_OE_OFFSET 0x14a
> +#define PCIE_DEBOUNCE_PARAM 0xF0F400
> +#define PCIE_OE_BYPASS (0x3 << 28)
> +
> +/* peri_crg ctrl */
> +#define CRGCTRL_PCIE_ASSERT_OFFSET 0x88
> +#define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000
> +
> +/* Time for delay */
> +#define REF_2_PERST_MIN 20000
> +#define REF_2_PERST_MAX 25000
> +#define PERST_2_ACCESS_MIN 10000
> +#define PERST_2_ACCESS_MAX 12000
> +#define LINK_WAIT_MIN 900
> +#define LINK_WAIT_MAX 1000
> +#define PIPE_CLK_WAIT_MIN 550
> +#define PIPE_CLK_WAIT_MAX 600
> +
> +struct kirin_pcie {
> + struct dw_pcie *pci;
> + void __iomem *apb_base;
> + void __iomem *phy_base;
> + struct regmap *crgctrl;
> + struct regmap *sysctrl;
> + struct clk *apb_sys_clk;
> + struct clk *apb_phy_clk;
> + struct clk *phy_ref_clk;
> + struct clk *pcie_aclk;
> + struct clk *pcie_aux_clk;
> + int gpio_id_reset;
> +};
> +
> +/* Registers in PCIeCTRL */
> +static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->apb_base + reg);
> +}
> +
> +static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32
> reg)
> +{
> + return readl(kirin_pcie->apb_base + reg);
> +}
> +
> +/* Registers in PCIePHY */
> +static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
> + u32 val, u32 reg)
> +{
> + writel(val, kirin_pcie->phy_base + reg);
> +}
> +
> +static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32
> reg)
> +{
> + return readl(kirin_pcie->phy_base + reg);
> +}
> +
> +static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> +
> + kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
> + if (IS_ERR(kirin_pcie->phy_ref_clk))
> + return PTR_ERR(kirin_pcie->phy_ref_clk);
> +
> + kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
> + if (IS_ERR(kirin_pcie->pcie_aux_clk))
> + return PTR_ERR(kirin_pcie->pcie_aux_clk);
> +
> + kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
> + if (IS_ERR(kirin_pcie->apb_phy_clk))
> + return PTR_ERR(kirin_pcie->apb_phy_clk);
> +
> + kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
> + if (IS_ERR(kirin_pcie->apb_sys_clk))
> + return PTR_ERR(kirin_pcie->apb_sys_clk);
> +
> + kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
> + if (IS_ERR(kirin_pcie->pcie_aclk))
> + return PTR_ERR(kirin_pcie->pcie_aclk);
> +
> + return 0;
> +}
> +
> +static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> + struct platform_device *pdev)
> +{
> + struct resource *apb;
> + struct resource *phy;
> + struct resource *dbi;
> + struct device *dev = &pdev->dev;
> +
> + apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
> + kirin_pcie->apb_base = devm_ioremap_resource(dev, apb);
> + if (IS_ERR(kirin_pcie->apb_base))
> + return PTR_ERR(kirin_pcie->apb_base);
> +
> + phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
> + kirin_pcie->phy_base = devm_ioremap_resource(dev, phy);
> + if (IS_ERR(kirin_pcie->phy_base))
> + return PTR_ERR(kirin_pcie->phy_base);
> +
> + dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> + kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi);
> + if (IS_ERR(kirin_pcie->pci->dbi_base))
> + return PTR_ERR(kirin_pcie->pci->dbi_base);
> +
> + kirin_pcie->crgctrl =
> + syscon_regmap_lookup_by_compatible("hisilicon,hi3660-
> crgctrl");
> + if (IS_ERR(kirin_pcie->crgctrl))
> + return PTR_ERR(kirin_pcie->crgctrl);
> +
> + kirin_pcie->sysctrl =
> +
syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
> + if (IS_ERR(kirin_pcie->sysctrl))
> + return PTR_ERR(kirin_pcie->sysctrl);
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
> +{
> + u32 reg_val;
> + u32 time = PIPE_CLK_MAX_TRY_TIMES;
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_REF_PAD_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
> + reg_val &= ~PHY_PWR_DOWN_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
> + udelay(10);
> +
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> + reg_val &= ~PHY_RST_ACK_BIT;
> + kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> + usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
> + reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> + if (reg_val & PIPE_CLK_STABLE) {
> + dev_err(kirin_pcie->pci->dev, "PIPE clk is not stable\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
> +{
> + u32 val;
> +
> + regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
> + val |= PCIE_DEBOUNCE_PARAM;
> + val &= ~PCIE_OE_BYPASS;
> + regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
> +}
> +
> +static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool
enable)
> +{
> + int ret = 0;
> +
> + if (!enable)
> + goto close_clk;
> +
> + ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
> + if (ret)
> + goto apb_sys_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
> + if (ret)
> + goto apb_phy_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
> + if (ret)
> + goto aclk_fail;
> +
> + ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
> + if (ret)
> + goto aux_clk_fail;
> +
> + return 0;
> +
> +close_clk:
> + clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
> +aux_clk_fail:
> + clk_disable_unprepare(kirin_pcie->pcie_aclk);
> +aclk_fail:
> + clk_disable_unprepare(kirin_pcie->apb_phy_clk);
> +apb_phy_fail:
> + clk_disable_unprepare(kirin_pcie->apb_sys_clk);
> +apb_sys_fail:
> + clk_disable_unprepare(kirin_pcie->phy_ref_clk);
> +
> + return ret;
> +}
> +
> +static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
> +{
> + int ret;
> +
> + /* Power supply for Host */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
> + udelay(100);
> + kirin_pcie_oe_enable(kirin_pcie);
> +
> + ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
> + if (ret)
> + return ret;
> +
> + /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
> + regmap_write(kirin_pcie->crgctrl,
> + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
> + regmap_write(kirin_pcie->sysctrl,
> + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
> +
> + ret = kirin_pcie_phy_init(kirin_pcie);
> + if (ret)
> + goto close_clk;
> +
> + /* perst assert Endpoint */
> + if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
> + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
> + ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
> + if (ret)
> + goto close_clk;
> + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
> +
> + return 0;
> + }
> +
> +close_clk:
> + kirin_pcie_clk_ctrl(kirin_pcie, false);
> + return ret;
> +}
> +
> +static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
> +}
> +
> +static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
> + bool on)
> +{
> + u32 val;
> +
> + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
> + if (on)
> + val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> + else
> + val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
> +}
> +
> +static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
> + int where, int size, u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + int ret;
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + ret = dw_pcie_read(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
> + int where, int size, u32 val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + int ret;
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + ret = dw_pcie_write(pci->dbi_base + where, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + u32 ret;
> +
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> + dw_pcie_read(base + reg, size, &ret);
> + kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> + return ret;
> +}
> +
> +static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> + u32 reg, size_t size, u32 val)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> + dw_pcie_write(base + reg, size, val);
> + kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +}
> +
> +static int kirin_pcie_link_up(struct dw_pcie *pci)
> +{
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> +
> + if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
> + return 1;
> +
> + return 0;
> +}
> +
> +static int kirin_pcie_establish_link(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> + int count = 0;
> +
> + if (kirin_pcie_link_up(pci))
> + return 0;
> +
> + dw_pcie_setup_rc(pp);
> +
> + /* assert LTSSM enable */
> + kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
> + PCIE_APP_LTSSM_ENABLE);
> +
> + /* check if the link is up or not */
> + while (!kirin_pcie_link_up(pci)) {
> + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> + count++;
> + if (count == 1000) {
> + dev_err(pci->dev, "Link Fail\n");
> + return -EINVAL;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static void kirin_pcie_host_init(struct pcie_port *pp)
> +{
> + kirin_pcie_establish_link(pp);
> +}
> +
> +static struct dw_pcie_ops kirin_dw_pcie_ops = {
> + .read_dbi = kirin_pcie_read_dbi,
> + .write_dbi = kirin_pcie_write_dbi,
> + .link_up = kirin_pcie_link_up,
> +};
> +
> +static struct dw_pcie_host_ops kirin_pcie_host_ops = {
> + .rd_own_conf = kirin_pcie_rd_own_conf,
> + .wr_own_conf = kirin_pcie_wr_own_conf,
> + .host_init = kirin_pcie_host_init,
> +};
> +
> +static int __init kirin_add_pcie_port(struct dw_pcie *pci,
> + struct platform_device *pdev)
> +{
> + pci->pp.ops = &kirin_pcie_host_ops;
> +
> + return dw_pcie_host_init(&pci->pp);
> +}
> +
> +static int kirin_pcie_probe(struct platform_device *pdev)
> +{
> + struct kirin_pcie *kirin_pcie;
> + struct dw_pcie *pci;
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + if (!dev->of_node) {
> + dev_err(&pdev->dev, "NULL node\n");
> + return -EINVAL;
> + }
> +
> + kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie),
> GFP_KERNEL);
> + if (!kirin_pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + pci->dev = dev;
> + pci->ops = &kirin_dw_pcie_ops;
> + kirin_pcie->pci = pci;
> +
> + ret = kirin_pcie_get_clk(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + ret = kirin_pcie_get_resource(kirin_pcie, pdev);
> + if (ret)
> + return ret;
> +
> + kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
> + "reset-gpio", 0);
> + if (kirin_pcie->gpio_id_reset < 0)
> + return -ENODEV;
> +
> + ret = kirin_pcie_power_on(kirin_pcie);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, kirin_pcie);
> +
> + return kirin_add_pcie_port(pci, pdev);
> +}
> +
> +static const struct of_device_id kirin_pcie_match[] = {
> + { .compatible = "hisilicon,kirin960-pcie" },
> + {},
> +};
> +
> +struct platform_driver kirin_pcie_driver = {
> + .probe = kirin_pcie_probe,
> + .driver = {
> + .name = "kirin-pcie",
> + .of_match_table = kirin_pcie_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +
> +builtin_platform_driver(kirin_pcie_driver);
> --
> 2.11.GIT
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