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[PATCH v5 0/3] ARM: dts: imx7: add NAND support

Started byStefan Agner <stefan@agner.ch>
First post2017-06-06 08:40 +0200
Last post2017-06-06 18:40 +0200
Articles 6 — 3 participants

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  [PATCH v5 0/3] ARM: dts: imx7: add NAND support Stefan Agner <stefan@agner.ch> - 2017-06-06 08:40 +0200
    [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA Stefan Agner <stefan@agner.ch> - 2017-06-06 08:40 +0200
      Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA Fabio Estevam <festevam@gmail.com> - 2017-06-06 18:40 +0200
      Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA Han Xu <han.xu@nxp.com> - 2017-06-07 17:40 +0200
    [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate Stefan Agner <stefan@agner.ch> - 2017-06-06 08:40 +0200
      Re: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate Fabio Estevam <festevam@gmail.com> - 2017-06-06 18:40 +0200

#1658393 — [PATCH v5 0/3] ARM: dts: imx7: add NAND support

FromStefan Agner <stefan@agner.ch>
Date2017-06-06 08:40 +0200
Subject[PATCH v5 0/3] ARM: dts: imx7: add NAND support
Message-ID<tPgjL-58I-5@gated-at.bofh.it>
This revision alters the clock tree such that the clock required by
the APBH DMA (NAND_USDHC_BUS_CLK_ROOT _after_ gate CCGR20) is available
as an independent clock.

So far the gate CCGR20 was used by the NAND_ROOT_CLK only. A previous
patch added the NAND_ROOT_CLK which also lead to the effect that the
clock gate CCGR20 gets enabled:
https://patchwork.ozlabs.org/patch/551967/

The data sheet seems to indicate that the APBH DMA only uses hclk which
is connected to NAND_USDHC_BUS_CLK_ROOT through gate CCGR20. Tests
seem to confirm this wiring.

By adding a new clock IMX7D_NAND_USDHC_BUS_RAWNAND_CLK we can assign
a clock which also enables the shared CCGR20 gate without changing the
DMA driver. This better reflects the true wiring and encapsulates the
SoC specific clock wiring in the clock tree instead leaking it into
the driver code.

Versions 2 and earlier also included NAND driver changes, which are
already merged.

--
Stefan

Changes since v4:
- Introduce *_RAWNAND_CLK which represent clocks after CCGR20
-
- Add assigned-clocks to set a reasonable parent for raw NAND

Changes since v3:
- Only specify IMX7D_NAND_USDHC_BUS_ROOT_CLK which seems to be sufficent

Changes since v2:
- Dropped driver changes, alreay merged

Changes since v1:
- Make clks_count const
- Introduce IS_IMX7D for i.MX 7 SoC's and make it part of GPMI_IS_MX6

Stefan Agner (3):
  clk: imx7d: create clocks behind rawnand clock gate
  ARM: dts: imx7: add GPMI NAND and APBH DMA
  ARM: dts: imx7-colibri: add NAND support

 arch/arm/boot/dts/imx7-colibri.dtsi     |  9 +++++++-
 arch/arm/boot/dts/imx7s.dtsi            | 32 ++++++++++++++++++++++++++-
 drivers/clk/imx/clk-imx7d.c             |  6 +++--
 include/dt-bindings/clock/imx7d-clock.h |  4 ++-
 4 files changed, 48 insertions(+), 3 deletions(-)

base-commit: e2bb3be2c6c623ff0bad975dc9435531f450f0c5
-- 
git-series 0.9.1

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#1658394 — [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA

FromStefan Agner <stefan@agner.ch>
Date2017-06-06 08:40 +0200
Subject[PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA
Message-ID<tPgjL-58I-15@gated-at.bofh.it>
In reply to#1658393
Add i.MX 7 APBH DMA and GPMI NAND modules.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index c4f12fd..d71acd8 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -995,5 +995,37 @@
 				status = "disabled";
 			};
 		};
+
+		dma_apbh: dma-apbh@33000000 {
+			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+			reg = <0x33000000 0x2000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+			clock-names = "dma_apbh_bch", "dma_apbh_io";
+		};
+
+		gpmi: gpmi-nand@33002000{
+			compatible = "fsl,imx7d-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "bch";
+			clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+				<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+			clock-names = "gpmi_io", "gpmi_bch_apb";
+			dmas = <&dma_apbh 0>;
+			dma-names = "rx-tx";
+			status = "disabled";
+			assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+		};
 	};
 };
-- 
git-series 0.9.1

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#1658932 — Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA

FromFabio Estevam <festevam@gmail.com>
Date2017-06-06 18:40 +0200
SubjectRe: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA
Message-ID<tPpGq-2N6-23@gated-at.bofh.it>
In reply to#1658394
On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote:
> Add i.MX 7 APBH DMA and GPMI NAND modules.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Tested on a imx7d-sdb:

[    1.303543] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd5
[    1.309999] nand: Samsung NAND 2GiB 3,3V 8-bit
[    1.314467] nand: 2048 MiB, MLC, erase size: 256 KiB, page size:
2048, OOB size: 64
[    1.346007] gpmi-nand 33002000.gpmi-nand: driver registered.

Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

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#1659934 — Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA

FromHan Xu <han.xu@nxp.com>
Date2017-06-07 17:40 +0200
SubjectRe: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA
Message-ID<tPLdT-8rQ-9@gated-at.bofh.it>
In reply to#1658394

On 06/06/2017 01:30 AM, Stefan Agner wrote:
> Add i.MX 7 APBH DMA and GPMI NAND modules.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>   arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index c4f12fd..d71acd8 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -995,5 +995,37 @@
>   				status = "disabled";
>   			};
>   		};
> +
> +		dma_apbh: dma-apbh@33000000 {
> +			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
> +			reg = <0x33000000 0x2000>;
> +			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
> +			#dma-cells = <1>;
> +			dma-channels = <4>;
> +			clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
> +			clock-names = "dma_apbh_bch", "dma_apbh_io";

please remove the clock names, I am good with all other changes.

> +		};
> +
> +		gpmi: gpmi-nand@33002000{
> +			compatible = "fsl,imx7d-gpmi-nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
> +			reg-names = "gpmi-nand", "bch";
> +			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "bch";
> +			clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
> +				<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
> +			clock-names = "gpmi_io", "gpmi_bch_apb";
> +			dmas = <&dma_apbh 0>;
> +			dma-names = "rx-tx";
> +			status = "disabled";
> +			assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
> +			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
> +		};
>   	};
>   };

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#1658396 — [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate

FromStefan Agner <stefan@agner.ch>
Date2017-06-06 08:40 +0200
Subject[PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate
Message-ID<tPgjM-58I-19@gated-at.bofh.it>
In reply to#1658393
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.

Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/clk/imx/clk-imx7d.c             | 6 ++++--
 include/dt-bindings/clock/imx7d-clock.h | 4 +++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 93b0364..e364060 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -25,6 +25,7 @@
 static u32 share_count_sai1;
 static u32 share_count_sai2;
 static u32 share_count_sai3;
+static u32 share_count_nand;
 
 static struct clk_div_table test_div_table[] = {
 	{ .val = 3, .div = 1, },
@@ -748,7 +749,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
 	clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
 	clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
-	clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6);
+	clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
 	clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
 	clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6);
 	clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6);
@@ -825,7 +826,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);
 	clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0);
 	clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
-	clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0);
+	clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand);
+	clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand);
 	clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);
 	clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0);
 	clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0);
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index a7a1a50..de62a83 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -450,5 +450,7 @@
 #define IMX7D_CLK_ARM			437
 #define IMX7D_CKIL			438
 #define IMX7D_OCOTP_CLK			439
-#define IMX7D_CLK_END			440
+#define IMX7D_NAND_RAWNAND_CLK		440
+#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
+#define IMX7D_CLK_END			442
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
-- 
git-series 0.9.1

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#1658928 — Re: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate

FromFabio Estevam <festevam@gmail.com>
Date2017-06-06 18:40 +0200
SubjectRe: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate
Message-ID<tPpGp-2N6-5@gated-at.bofh.it>
In reply to#1658396
On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote:
> The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
> and NAND_CLK_ROOT. However, the gate has been in the chain of the
> latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
> only, e.g. as required by APBH-Bridge-DMA.
>
> Add new clocks which represent the clock after the gate, and use a
> shared clock gate to correctly model the hardware.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

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