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[PATCH v2 00/11] ARC plat-eznps upstream cont.

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  [PATCH v2 00/11] ARC plat-eznps upstream cont. Noam Camus <noamca@mellanox.com> - 2017-05-28 09:00 +0200
    [PATCH v2 05/11] ARC: [plat-eznps] typo fix at Kconfig Noam Camus <noamca@mellanox.com> - 2017-05-28 09:00 +0200
    [PATCH v2 06/11] ARC: [plat-eznps] Fix TLB Errata Noam Camus <noamca@mellanox.com> - 2017-05-28 09:00 +0200
    [PATCH v2 01/11] ARC: set level of log per CPU during boot to be debug level Noam Camus <noamca@mellanox.com> - 2017-05-28 09:00 +0200
    [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception Noam Camus <noamca@mellanox.com> - 2017-05-28 09:00 +0200
      Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an  exception Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-06-02 21:10 +0200
        RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an  exception Noam Camus <noamca@mellanox.com> - 2017-06-04 08:20 +0200
      Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an  exception Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-06-07 00:20 +0200
        RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an  exception Noam Camus <noamca@mellanox.com> - 2017-06-07 08:10 +0200
        RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an  exception Noam Camus <noamca@mellanox.com> - 2017-06-07 13:20 +0200
          Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an  exception Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-06-07 18:20 +0200
    [PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault Noam Camus <noamca@mellanox.com> - 2017-05-28 09:00 +0200
      Re: [PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in  case of page fault Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-05-30 18:50 +0200

#1652039 — [PATCH v2 00/11] ARC plat-eznps upstream cont.

From: Noam Camus <noamca@mellanox.com>

Change Log
-----------
v1 --> v2:
Outcome of Alexey Brodkin comments
1) Turned mem_service into weak symbol, so it can be override
by any platform
2) remove ifedf wrapper on '88' lable at assembly of TLB exception.


With this patch set I continue the effort of upstreaming the
eznps platform for arch/arc.

it combine of patches for typos and other for HW erratas and some
for performance.
All selected as ones that may be obvious for merge with arc next.

This was based on for-curr branch as the mos updated one I found
at this point of time. 

Liav Rehana (2):
  ARC: typo fix in mm/fault.c
  ARC: typos fix in kernel/entry-compact.S

Noam Camus (9):
  ARC: set level of log per CPU during boot to be debug level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: [plat-eznps] typo fix at Kconfig
  ARC: [plat-eznps] Fix TLB Errata
  ARC: [plat-eznps] disabled stall counter due to a HW bug
  ARC: [plat-eznps] spinlock aware for MTM
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle
    task
  ARC: enable platform specific mem_service implementation
  ARC: [plat-eznps] Handle memory error as an exception

 arch/arc/include/asm/cacheflush.h       |    3 ++-
 arch/arc/include/asm/spinlock.h         |    6 ++++++
 arch/arc/kernel/entry-compact.S         |   25 +++++++++++++------------
 arch/arc/kernel/process.c               |    7 +++++++
 arch/arc/kernel/setup.c                 |    6 +++---
 arch/arc/kernel/smp.c                   |    4 ++--
 arch/arc/mm/cache.c                     |   14 +++++++++++---
 arch/arc/mm/fault.c                     |    2 +-
 arch/arc/mm/tlb.c                       |    4 ++--
 arch/arc/mm/tlbex.S                     |    9 +++++++++
 arch/arc/plat-eznps/Kconfig             |   15 +++++++++++++--
 arch/arc/plat-eznps/entry.S             |   14 ++++++++++++++
 arch/arc/plat-eznps/include/plat/ctop.h |    1 +
 arch/arc/plat-eznps/mtm.c               |    2 --
 14 files changed, 84 insertions(+), 28 deletions(-)

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#1652040 — [PATCH v2 05/11] ARC: [plat-eznps] typo fix at Kconfig

From: Noam Camus <noamca@mellanox.com>

Signed-off-by: Noam Camus <noamca@mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
---
 arch/arc/plat-eznps/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -12,8 +12,8 @@ menuconfig ARC_PLAT_EZNPS
 	help
 	  Support for EZchip development platforms,
 	  based on ARC700 cores.
-	  We handle few flavours:
-	    - Hardware Emulator AKA HE which is FPGA based chasis
+	  We handle few flavors:
+	    - Hardware Emulator AKA HE which is FPGA based chassis
 	    - Simulator based on MetaWare nSIM
 	    - NPS400 chip based on ASIC
 
-- 
1.7.1

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#1652041 — [PATCH v2 06/11] ARC: [plat-eznps] Fix TLB Errata

From: Noam Camus <noamca@mellanox.com>

Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/mm/tlbex.S |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index b30e4e3..0e1e47a 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+	/* verify if entry for this vaddr+ASID already exists */
+	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
+	lr    r0, [ARC_REG_TLBINDEX]
+	bbit0 r0, 31, 88f
+#endif
+
 	/* Get free TLB slot: Set = computed from vaddr, way = random */
 	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,8 @@ ex_saved_reg1:
 #else
 	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+
+88:
 .endm
 
 
-- 
1.7.1

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#1652042 — [PATCH v2 01/11] ARC: set level of log per CPU during boot to be debug level

From: Noam Camus <noamca@mellanox.com>

The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/kernel/setup.c |    6 +++---
 arch/arc/kernel/smp.c   |    4 ++--
 arch/arc/mm/cache.c     |    2 +-
 arch/arc/mm/tlb.c       |    2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
 	read_arc_build_cfg_regs();
 	arc_init_IRQ();
 
-	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+	pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
 	arc_mmu_init();
 	arc_cache_init();
 
-	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-	printk(arc_platform_smp_cpuinfo());
+	pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+	pr_debug("%s", arc_platform_smp_cpuinfo());
 
 	arc_chk_core_config();
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 
 	secondary_idle_tsk = idle;
 
-	pr_info("Idle Task [%d] %p", cpu, idle);
-	pr_info("Trying to bring up CPU%u ...\n", cpu);
+	pr_debug("Idle Task [%d] %p", cpu, idle);
+	pr_debug("Trying to bring up CPU%u ...\n", cpu);
 
 	if (plat_smp_ops.cpu_kick)
 		plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..7d3e79b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
 	unsigned int __maybe_unused cpu = smp_processor_id();
 	char str[256];
 
-	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+	pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
 	/*
 	 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
 	char str[256];
 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
 
-	printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+	pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
 	/*
 	 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1

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#1652043 — [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

From: Noam Camus <noamca@mellanox.com>

This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
We override weak symbole of mem_service to achieve that.

Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++++++++++
 arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..c5f946c 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
 	  any of them seem like CPU from Linux point of view.
 	  All threads within same core share the execution unit of the
 	  core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR
+       bool "ARC-EZchip Memory error as an exception"
+       depends on ARC_PLAT_EZNPS
+       default n
+       help
+         On the real chip of the NPS, user memory errors are handled
+         as a machine check exception, whereas on simulator platform
+         for NPS, it handled as an interrupt level 2 (like legacy arc
+         real chip architecture).This configuration will cause the kernel
+         to handle memory error as a machine check exception.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c..03e2892 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -68,3 +68,17 @@ ENTRY(res_service)
 
 	j	stext
 END(res_service)
+
+#if defined(CONFIG_EZNPS_MEM_ERROR)
+ENTRY(mem_service)
+	; SW workaround to cover up on a difference between
+	; NPS real chip and simulator behaviors.
+	; NPS real chip will activate a machine check exception
+	; in case of memory error, while the simulator will
+	; trigger a level 2 interrupt. Therefor this code section
+	; should be reached only in simulation mode.
+	; DEAD END: display Regs and HALT
+
+	j EV_MachineCheck
+END(mem_service)
+#endif
-- 
1.7.1

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#1656476 — Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> We override weak symbole of mem_service to achieve that.
> 
> Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>   arch/arc/plat-eznps/Kconfig |   11 +++++++++++
>   arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
> index feaa471..c5f946c 100644
> --- a/arch/arc/plat-eznps/Kconfig
> +++ b/arch/arc/plat-eznps/Kconfig
> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>   	  any of them seem like CPU from Linux point of view.
>   	  All threads within same core share the execution unit of the
>   	  core and HW scheduler round robin between them.
> +
> +config EZNPS_MEM_ERROR
> +       bool "ARC-EZchip Memory error as an exception"
> +       depends on ARC_PLAT_EZNPS
> +       default n
> +       help
> +         On the real chip of the NPS, user memory errors are handled
> +         as a machine check exception, whereas on simulator platform
> +         for NPS, it handled as an interrupt level 2 (like legacy arc
> +         real chip architecture).This configuration will cause the kernel
> +         to handle memory error as a machine check exception.

Do you really need a Kconfig option here. AFAIKR you guys had some magic in 
platform code to determine whether running on sim or hw - can that be not used ?

> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
> index 328261c..03e2892 100644
> --- a/arch/arc/plat-eznps/entry.S
> +++ b/arch/arc/plat-eznps/entry.S
> @@ -68,3 +68,17 @@ ENTRY(res_service)
>   
>   	j	stext
>   END(res_service)
> +
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +ENTRY(mem_service)
> +	; SW workaround to cover up on a difference between
> +	; NPS real chip and simulator behaviors.
> +	; NPS real chip will activate a machine check exception
> +	; in case of memory error, while the simulator will
> +	; trigger a level 2 interrupt. Therefor this code section
> +	; should be reached only in simulation mode.
> +	; DEAD END: display Regs and HALT
> +
> +	j EV_MachineCheck
> +END(mem_service)
> +#endif


Just squash the weak symbol patch in here - not worth a separate patch !

-Vineet

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#1656998 — RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

> From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
> Sent: Friday, June 2, 2017 22:04 PM

>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig 
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>>   	  any of them seem like CPU from Linux point of view.
>>   	  All threads within same core share the execution unit of the
>>   	  core and HW scheduler round robin between them.
>> +
>> +config EZNPS_MEM_ERROR
>> +       bool "ARC-EZchip Memory error as an exception"
>> +       depends on ARC_PLAT_EZNPS
>> +       default n
>> +       help
>> +         On the real chip of the NPS, user memory errors are handled
>> +         as a machine check exception, whereas on simulator platform
>> +         for NPS, it handled as an interrupt level 2 (like legacy arc
>> +         real chip architecture).This configuration will cause the kernel
>> +         to handle memory error as a machine check exception.

>Do you really need a Kconfig option here. AFAIKR you guys had some magic in platform code to determine whether running on sim or hw - can that be not used ?
We do not have this anymore, needed to create dedicated one here.

...

>> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S 
>> index 328261c..03e2892 100644
>> --- a/arch/arc/plat-eznps/entry.S
>> +++ b/arch/arc/plat-eznps/entry.S
>> @@ -68,3 +68,17 @@ ENTRY(res_service)
>>   
>>   	j	stext
>>   END(res_service)
>> +
>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>> +ENTRY(mem_service)
>> +	; SW workaround to cover up on a difference between
>> +	; NPS real chip and simulator behaviors.
>> +	; NPS real chip will activate a machine check exception
>> +	; in case of memory error, while the simulator will
>> +	; trigger a level 2 interrupt. Therefor this code section
>> +	; should be reached only in simulation mode.
>> +	; DEAD END: display Regs and HALT
>> +
>> +	j EV_MachineCheck
>> +END(mem_service)
>> +#endif


>Just squash the weak symbol patch in here - not worth a separate patch !
Ok , no problem.

-Noam

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#1659257 — Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 05/27/2017 11:52 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
> If set, it will cause the kernel to handle user memory error
> as a machine check exception.
> It is required in order to align the NPS simulator memory
> error handling to the one of the NPS400 real chip behavior.
> We override weak symbole of mem_service to achieve that.
> 
> Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> ---
>   arch/arc/plat-eznps/Kconfig |   11 +++++++++++
>   arch/arc/plat-eznps/entry.S |   14 ++++++++++++++
>   2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
> index feaa471..c5f946c 100644
> --- a/arch/arc/plat-eznps/Kconfig
> +++ b/arch/arc/plat-eznps/Kconfig
> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>   	  any of them seem like CPU from Linux point of view.
>   	  All threads within same core share the execution unit of the
>   	  core and HW scheduler round robin between them.
> +
> +config EZNPS_MEM_ERROR
> +       bool "ARC-EZchip Memory error as an exception"
> +       depends on ARC_PLAT_EZNPS
> +       default n

So you set default to "n" - thus by default it works for the simulator not silicon ?


> +       help
> +         On the real chip of the NPS, user memory errors are handled
> +         as a machine check exception, whereas on simulator platform
> +         for NPS, it handled as an interrupt level 2 (like legacy arc
> +         real chip architecture).This configuration will cause the kernel
> +         to handle memory error as a machine check exception.
> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
> index 328261c..03e2892 100644
> --- a/arch/arc/plat-eznps/entry.S
> +++ b/arch/arc/plat-eznps/entry.S
> @@ -68,3 +68,17 @@ ENTRY(res_service)
>   
>   	j	stext
>   END(res_service)
> +
> +#if defined(CONFIG_EZNPS_MEM_ERROR)
> +ENTRY(mem_service)
> +	; SW workaround to cover up on a difference between
> +	; NPS real chip and simulator behaviors.
> +	; NPS real chip will activate a machine check exception
> +	; in case of memory error, while the simulator will
> +	; trigger a level 2 interrupt. Therefor this code section
> +	; should be reached only in simulation mode.
> +	; DEAD END: display Regs and HALT
> +
> +	j EV_MachineCheck
> +END(mem_service)
> +#endif
> 

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#1659391 — RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

>From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
>Sent: Wednesday, June 7, 2017 1:11 AM
...
>> +
>> +config EZNPS_MEM_ERROR
>> +       bool "ARC-EZchip Memory error as an exception"
>> +       depends on ARC_PLAT_EZNPS
>> +       default n

>So you set default to "n" - thus by default it works for the simulator not silicon ?
Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.

-Noam

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#1659690 — RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

> From: Noam Camus 
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' <Vineet.Gupta1@synopsys.com>; linux-snps-arc@lists.infradead.org
>Cc: linux-kernel@vger.kernel.org; Elad Kanfi <eladkan@mellanox.com>
>Subject: RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

>>From: Vineet Gupta [mailto:Vineet.Gupta1@synopsys.com] 
>>Sent: Wednesday, June 7, 2017 1:11 AM
>...
>>> +
>>> +config EZNPS_MEM_ERROR
>>> +       bool "ARC-EZchip Memory error as an exception"
>>> +       depends on ARC_PLAT_EZNPS
>>> +       default n

>>So you set default to "n" - thus by default it works for the simulator not silicon ?
>Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.

Sorry, but It is not correct.
Default is for silicon where it is naturally emits machine check and unlike simulator do not need OS to redirect the ISR L2 to machine check handler.
Above motivation of "align" is true, but default is silicon and not sim, as I wrote in my original configuration help.
Please re-update this CONFIG help section.

Thanks
-Noam

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#1659975 — Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

On 06/07/2017 04:14 AM, Noam Camus wrote:
>>>> +config EZNPS_MEM_ERROR
>>>> +       bool "ARC-EZchip Memory error as an exception"
>>>> +       depends on ARC_PLAT_EZNPS
>>>> +       default n
>>> So you set default to "n" - thus by default it works for the simulator not silicon ?
>> Correct, this way I "align" Sim environment to react as close as possible to how it work with silicon.
> Sorry, but It is not correct.
> Default is for silicon where it is naturally emits machine check and unlike simulator do not need OS to redirect the ISR L2 to machine check handler.
> Above motivation of "align" is true, but default is silicon and not sim, as I wrote in my original configuration help.
> Please re-update this CONFIG help section.



So NPS *hardware* generates exception, jumps to vector mem_service(), which you 
redirect to the machine check handler - which simply panics.
But this redirection is under EZNPS_MEM_ERROR, which you have defaulted to "n". So 
how is the default working for hardware ? Doesn't it need to be "y"

BTW it seems your patch is wrong otherwise too. So the userspace bus error will go 
to machine check handler which currently just panic's. You really want to kill the 
user space process and continue, thus need to call do_memory_error()

-Vineet

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#1652044 — [PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

From: Noam Camus <noamca@mellanox.com>

This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.

Signed-off-by: Noam Camus <noamca@mellanox.com>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
---
 arch/arc/include/asm/cacheflush.h |    3 ++-
 arch/arc/mm/cache.c               |   12 ++++++++++--
 arch/arc/mm/tlb.c                 |    2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
 
 void flush_icache_range(unsigned long kstart, unsigned long kend);
 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr);
 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7d3e79b..e1ea57f 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
 }
 
 /* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+		       phys_addr_t paddr, unsigned long vaddr)
 {
-	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+	struct ic_inv_args ic_inv = {
+		.paddr	= paddr,
+		.vaddr	= vaddr,
+		.sz	= PAGE_SIZE
+	};
+
+	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
 }
 
 /*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index c5e70d8..a095608 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 
 			/* invalidate any existing icache lines (U-mapping) */
 			if (vma->vm_flags & VM_EXEC)
-				__inv_icache_page(paddr, vaddr);
+				__inv_icache_page(vma, paddr, vaddr);
 		}
 	}
 }
-- 
1.7.1

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#1653381 — Re: [PATCH v2 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

On 05/27/2017 11:51 PM, Noam Camus wrote:
> From: Noam Camus <noamca@mellanox.com>
> 
> This patch is derived due to performance issue.
> The use case is a page fault that resides on more than the local cpu.
> Trying to broadcast all CPUs results on performance degradation.
> So we try to avoid this by sending only to the relevant CPUs.
> 
> Signed-off-by: Noam Camus <noamca@mellanox.com>
> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>

This indeed looks like a nice optimization - do you have any performance numbers 
when say running hackbench or other multi-threaded workloads !

-Vineet

> ---
>   arch/arc/include/asm/cacheflush.h |    3 ++-
>   arch/arc/mm/cache.c               |   12 ++++++++++--
>   arch/arc/mm/tlb.c                 |    2 +-
>   3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
> index fc662f4..716dba1 100644
> --- a/arch/arc/include/asm/cacheflush.h
> +++ b/arch/arc/include/asm/cacheflush.h
> @@ -33,7 +33,8 @@
>   
>   void flush_icache_range(unsigned long kstart, unsigned long kend);
>   void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
> -void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
> +void __inv_icache_page(struct vm_area_struct *vma,
> +		       phys_addr_t paddr, unsigned long vaddr);
>   void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
>   
>   #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
> diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
> index 7d3e79b..e1ea57f 100644
> --- a/arch/arc/mm/cache.c
> +++ b/arch/arc/mm/cache.c
> @@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len)
>   }
>   
>   /* wrapper to compile time eliminate alignment checks in flush loop */
> -void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
> +void __inv_icache_page(struct vm_area_struct *vma,
> +		       phys_addr_t paddr, unsigned long vaddr)
>   {
> -	__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
> +	struct ic_inv_args ic_inv = {
> +		.paddr	= paddr,
> +		.vaddr	= vaddr,
> +		.sz	= PAGE_SIZE
> +	};
> +
> +	on_each_cpu_mask(mm_cpumask(vma->vm_mm),
> +			 __ic_line_inv_vaddr_helper, &ic_inv, 1);
>   }
>   
>   /*
> diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
> index c5e70d8..a095608 100644
> --- a/arch/arc/mm/tlb.c
> +++ b/arch/arc/mm/tlb.c
> @@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
>   
>   			/* invalidate any existing icache lines (U-mapping) */
>   			if (vma->vm_flags & VM_EXEC)
> -				__inv_icache_page(paddr, vaddr);
> +				__inv_icache_page(vma, paddr, vaddr);
>   		}
>   	}
>   }
> 

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