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[PATCHv2 0/2] gpio: mvebu: fixes for PWM/blink

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  [PATCHv2 0/2] gpio: mvebu: fixes for PWM/blink Richard Genoud <richard.genoud@gmail.com> - 2017-06-01 14:20 +0200
    [PATCHv2 2/2] gpio: mvebu: fix gpio bank registration when pwm is used Richard Genoud <richard.genoud@gmail.com> - 2017-06-01 14:20 +0200
      Re: [PATCHv2 2/2] gpio: mvebu: fix gpio bank registration when pwm is used Gregory CLEMENT <gregory.clement@free-electrons.com> - 2017-06-01 17:00 +0200
    [PATCHv2 1/2] gpio: mvebu: fix blink counter register selection Richard Genoud <richard.genoud@gmail.com> - 2017-06-01 14:20 +0200

#1655076 — [PATCHv2 0/2] gpio: mvebu: fixes for PWM/blink

These are 2 fixes for gpio-mvebu, related to the PWM support introduced
by commit 757642f9a584 ("gpio: mvebu: Add limited PWM support")
As that commit was merged in 4.12-rc1, I guess these commits are 4.12
material.

Changes from v1:
 - Add tags Fixes: and Reviewed-by:
 - Add some comments to motivate the mvpwm->chip->base = -1 choice
instead of mvpwm->chip->base = mvchip->chip.base

Richard Genoud (2):
  gpio: mvebu: fix blink counter register selection
  gpio: mvebu: fix gpio bank registration when pwm is used

 drivers/gpio/gpio-mvebu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

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#1655079 — [PATCHv2 2/2] gpio: mvebu: fix gpio bank registration when pwm is used

If more than one gpio bank has the "pwm" property, only one will be
registered successfully, all the others will fail with:
mvebu-gpio: probe of f1018140.gpio failed with error -17

That's because in alloc_pwms(), the chip->base (aka "int pwm"), was not
set (thus, ==0) ; and 0 is a meaningful start value in alloc_pwm().
What was intended is mvpwm->chip->base = -1.
Like that, the numbering will be done auto-magically

Moreover, as the region might be already occupied by another pwm, we
shouldn't force:
mvpwm->chip->base = 0
nor
mvpwm->chip->base = id * MVEBU_MAX_GPIO_PER_BANK;

Tested on clearfog-pro (Marvell 88F6828)

Fixes: 757642f9a584 ("gpio: mvebu: Add limited PWM support")
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
---
 drivers/gpio/gpio-mvebu.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index cdef2c78cb3b..5104b6398139 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -768,6 +768,13 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
 	mvpwm->chip.dev = dev;
 	mvpwm->chip.ops = &mvebu_pwm_ops;
 	mvpwm->chip.npwm = mvchip->chip.ngpio;
+	/*
+	 * There may already be some PWM allocated, so we can't force
+	 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
+	 * So, we let pwmchip_add() do the numbering and take the next free
+	 * region.
+	 */
+	mvpwm->chip.base = -1;
 
 	spin_lock_init(&mvpwm->lock);
 

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#1655227 — Re: [PATCHv2 2/2] gpio: mvebu: fix gpio bank registration when pwm is used

Hi Richard,
 
 On jeu., juin 01 2017, Richard Genoud <richard.genoud@gmail.com> wrote:

> If more than one gpio bank has the "pwm" property, only one will be
> registered successfully, all the others will fail with:
> mvebu-gpio: probe of f1018140.gpio failed with error -17
>
> That's because in alloc_pwms(), the chip->base (aka "int pwm"), was not
> set (thus, ==0) ; and 0 is a meaningful start value in alloc_pwm().
> What was intended is mvpwm->chip->base = -1.
> Like that, the numbering will be done auto-magically
>
> Moreover, as the region might be already occupied by another pwm, we
> shouldn't force:
> mvpwm->chip->base = 0
> nor
> mvpwm->chip->base = id * MVEBU_MAX_GPIO_PER_BANK;
>
> Tested on clearfog-pro (Marvell 88F6828)
>
> Fixes: 757642f9a584 ("gpio: mvebu: Add limited PWM support")
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>

Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Thanks,

Gregory


> ---
>  drivers/gpio/gpio-mvebu.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
> index cdef2c78cb3b..5104b6398139 100644
> --- a/drivers/gpio/gpio-mvebu.c
> +++ b/drivers/gpio/gpio-mvebu.c
> @@ -768,6 +768,13 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
>  	mvpwm->chip.dev = dev;
>  	mvpwm->chip.ops = &mvebu_pwm_ops;
>  	mvpwm->chip.npwm = mvchip->chip.ngpio;
> +	/*
> +	 * There may already be some PWM allocated, so we can't force
> +	 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
> +	 * So, we let pwmchip_add() do the numbering and take the next free
> +	 * region.
> +	 */
> +	mvpwm->chip.base = -1;
>  
>  	spin_lock_init(&mvpwm->lock);
>  

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

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#1655080 — [PATCHv2 1/2] gpio: mvebu: fix blink counter register selection

The blink counter A was always selected because 0 was forced in the
blink select counter register.
The variable 'set' was obviously there to be used as the register value,
selecting the B counter when id==1 and A counter when id==0.

Tested on clearfog-pro (Marvell 88F6828)

Fixes: 757642f9a584 ("gpio: mvebu: Add limited PWM support")
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
---
 drivers/gpio/gpio-mvebu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 19a92efabbef..cdef2c78cb3b 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -747,7 +747,7 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
 		set = U32_MAX;
 	else
 		return -EINVAL;
-	writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip));
+	writel_relaxed(set, mvebu_gpioreg_blink_counter_select(mvchip));
 
 	mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
 	if (!mvpwm)

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