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| Started by | Mikko Perttunen <mperttunen@nvidia.com> |
|---|---|
| First post | 2017-06-01 10:10 +0200 |
| Last post | 2017-06-01 10:10 +0200 |
| Articles | 3 — 1 participant |
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[PATCH v2 0/2] Device tree changes for Tegra186 cpufreq Mikko Perttunen <mperttunen@nvidia.com> - 2017-06-01 10:10 +0200
[PATCH v2 2/2] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 Mikko Perttunen <mperttunen@nvidia.com> - 2017-06-01 10:10 +0200
[PATCH v2 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster Mikko Perttunen <mperttunen@nvidia.com> - 2017-06-01 10:10 +0200
| From | Mikko Perttunen <mperttunen@nvidia.com> |
|---|---|
| Date | 2017-06-01 10:10 +0200 |
| Subject | [PATCH v2 0/2] Device tree changes for Tegra186 cpufreq |
| Message-ID | <tNtl8-8tU-3@gated-at.bofh.it> |
Hi, these are the device tree and bindings changes for the Tegra186 cpufreq driver that was recently merged. The patches are the same as those that were originally posted with the driver. Mikko Perttunen (2): dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 17 +++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++++++ 2 files changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt -- 2.1.4
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| From | Mikko Perttunen <mperttunen@nvidia.com> |
|---|---|
| Date | 2017-06-01 10:10 +0200 |
| Subject | [PATCH v2 2/2] arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186 |
| Message-ID | <tNtl8-8tU-17@gated-at.bofh.it> |
| In reply to | #1654898 |
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 3ea5e6369bc3..c023af0be43d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -347,6 +347,13 @@
reg-names = "pmc", "wake", "aotag", "scratch";
};
+ ccplex@e000000 {
+ compatible = "nvidia,tegra186-ccplex-cluster";
+ reg = <0x0 0x0e000000 0x0 0x3fffff>;
+
+ nvidia,bpmp = <&bpmp>;
+ };
+
sysram@30000000 {
compatible = "nvidia,tegra186-sysram", "mmio-sram";
reg = <0x0 0x30000000 0x0 0x50000>;
--
2.1.4
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| From | Mikko Perttunen <mperttunen@nvidia.com> |
|---|---|
| Date | 2017-06-01 10:10 +0200 |
| Subject | [PATCH v2 1/2] dt-bindings: Add bindings for nvidia,tegra186-ccplex-cluster |
| Message-ID | <tNtl8-8tU-23@gated-at.bofh.it> |
| In reply to | #1654898 |
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped
registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
.../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
new file mode 100644
index 000000000000..e8fb416c892b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt
@@ -0,0 +1,17 @@
+NVIDIA Tegra CCPLEX_CLUSTER area
+
+Required properties:
+- compatible: Should contain one of the following:
+ - "nvidia,tegra186-ccplex-cluster": for Tegra186
+- reg: Must contain an (offset, length) pair of the device's MMIO
+ register area
+- nvidia,bpmp: phandle to BPMP device that can be queried for OPP tables
+
+Example:
+
+ ccplex@e000000 {
+ compatible = "nvidia,tegra186-ccplex-cluster";
+ reg = <0x0 0x0e000000 0x0 0x3fffff>,
+
+ nvidia,bpmp = <&bpmp>;
+ };
--
2.1.4
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