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Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

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  Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core  PLLs on ls1012a Stephen Boyd <sboyd@codeaurora.org> - 2017-06-01 10:30 +0200
    RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core  PLLs on ls1012a Andy Tang <andy.tang@nxp.com> - 2017-06-01 10:40 +0200
      Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core  PLLs on ls1012a Stephen Boyd <sboyd@codeaurora.org> - 2017-06-01 20:20 +0200

#1654920 — Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
> 
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1654933

Hi Stephen,

Thanks for your applying.

There are other two patches sent on April 6, 2017:
https://patchwork.kernel.org/patch/9665973/
https://patchwork.kernel.org/patch/9665977/

Hope they are in your review queue. Please give it a review.

Regards,
Andy

-----Original Message-----
From: Stephen Boyd [mailto:sboyd@codeaurora.org] 
Sent: Thursday, June 01, 2017 4:28 PM
To: Andy Tang <andy.tang@nxp.com>
Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood <oss@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@buserror.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the 
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will 
> be used for the core PLLs.
> 
> Signed-off-by: Scott Wood <oss@buserror.net>
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

Applied to clk-next

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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#1655655

On 06/01, Andy Tang wrote:
> Hi Stephen,
> 
> Thanks for your applying.
> 
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
> 
> Hope they are in your review queue. Please give it a review.
> 

Yep they're there. I need to go update patchwork so the queue can
be known outside my local inbox.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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