Groups > linux.kernel > #1652969 > unrolled thread

[GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86 due for the v4.13 merge window

Started by	Lee Jones <lee.jones@linaro.org>
First post	2017-05-30 11:00 +0200
Last post	2017-06-01 00:50 +0200
Articles	16 on this page of 36 — 8 participants

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.

  [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86 due  for the v4.13 merge window Lee Jones <lee.jones@linaro.org> - 2017-05-30 11:00 +0200
    Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Stephen Rothwell <sfr@canb.auug.org.au> - 2017-05-31 05:40 +0200
      Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-05-31 06:30 +0200
        Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Lee Jones <lee.jones@linaro.org> - 2017-05-31 09:00 +0200
          Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window sathyanarayanan kuppuswamy          <sathyanarayanan.kuppuswamy@linux.intel.com> - 2017-06-01 00:40 +0200
            Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Darren Hart <dvhart@infradead.org> - 2017-06-03 19:10 +0200
      Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-05-31 06:30 +0200
      Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Lee Jones <lee.jones@linaro.org> - 2017-05-31 09:00 +0200
    Re: [GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86  due for the v4.13 merge window Lee Jones <lee.jones@linaro.org> - 2017-05-31 09:10 +0200
      [PATCH v5 8/8] platform/x86: intel_bxtwc_tmu: Remove first level irq unmask sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
      [PATCH v5 4/8] mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
      [PATCH v5 6/8] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
        Re: [PATCH v5 6/8] mfd: intel_soc_pmic_bxtwc: Utilize devm_*  functions in driver probe Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 15:10 +0200
      [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
        Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level  PMIC thermal irq Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 15:10 +0200
          Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level  PMIC thermal irq Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-06-03 19:30 +0200
            Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level  PMIC thermal irq Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 19:40 +0200
              Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level  PMIC thermal irq Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@gmail.com> - 2017-06-03 20:00 +0200
                Re: [PATCH v5 3/8] thermal: intel_bxt_pmic_thermal: Use first level  PMIC thermal irq Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 20:20 +0200
                  [PATCH v6 6/6] platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                  [PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                  [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                    Re: [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for  second level IRQ chips Heikki Krogerus <heikki.krogerus@linux.intel.com> - 2017-06-06 11:40 +0200
                  [PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                  [PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                  [PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                  [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-05 21:20 +0200
                    Re: [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-06 11:40 +0200
      [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
        Re: [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 15:30 +0200
      [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
        Re: [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for  second level irq chips Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 15:30 +0200
      [PATCH v5 2/8] mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
      [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200
        Re: [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-06-03 15:10 +0200
      [PATCH v5 1/8] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index sathyanarayanan.kuppuswamy@linux.intel.com - 2017-06-01 00:50 +0200

Page 2 of 2 — ← Prev page 1 [2]

#1658084 — [PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-05 21:20 +0200
Subject	[PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
Message-ID	<tP5HI-6Wy-7@gated-at.bofh.it>
In reply to	#1656885

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Since all second level thermal IRQs are consumed by the same
device(bxt_wcove_thermal), there is no need to expose them as separate
interrupts. We can just export only the first level IRQs for thermal and
let the device(bxt_wcove_thermal) driver handle the second level IRQs
based on thermal interrupt status register. Also, just using only the
first level IRQ will eliminate the bug involved in requesting only the
second level IRQ and not explicitly enable the first level IRQ. For
more info on this issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

This patch also makes relevant change in bxt_wcove_thermal driver to use
only first level PMIC thermal IRQ.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Zhang Rui <rui.zhang@intel.com>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c       | 32 ++++++++++++--------------------
 drivers/thermal/intel_bxt_pmic_thermal.c |  2 +-
 2 files changed, 13 insertions(+), 21 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * Rebased on top of latest release.

Changes since v5:
 * Squashed intel_bxt_pmic_thermal driver patch.
 * Changed irq -> IRQ


diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7cbaf1e..7c1ed27 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -84,10 +84,7 @@ enum bxtwc_irqs {
 
 enum bxtwc_irqs_level2 {
 	/* Level 2 */
-	BXTWC_THRM0_IRQ = 0,
-	BXTWC_THRM1_IRQ,
-	BXTWC_THRM2_IRQ,
-	BXTWC_BCU_IRQ,
+	BXTWC_BCU_IRQ = 0,
 	BXTWC_ADC_IRQ,
 	BXTWC_USBC_IRQ,
 	BXTWC_CHGR0_IRQ,
@@ -114,17 +111,14 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
-	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
-	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
-	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
-	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
-	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
-	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
-	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
-	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
+	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
+	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
+	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
+	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
+	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
@@ -142,8 +136,8 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
 	.name = "bxtwc_irq_chip_level2",
-	.status_base = BXTWC_THRM0IRQ,
-	.mask_base = BXTWC_MTHRM0IRQ,
+	.status_base = BXTWC_BCUIRQ,
+	.mask_base = BXTWC_MBCUIRQ,
 	.irqs = bxtwc_regmap_irqs_level2,
 	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
 	.num_regs = 10,
@@ -177,9 +171,7 @@ static struct resource charger_resources[] = {
 };
 
 static struct resource thermal_resources[] = {
-	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
-	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
-	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
+	DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 };
 
 static struct resource bcu_resources[] = {
diff --git a/drivers/thermal/intel_bxt_pmic_thermal.c b/drivers/thermal/intel_bxt_pmic_thermal.c
index 0f19a39..ef6b322 100644
--- a/drivers/thermal/intel_bxt_pmic_thermal.c
+++ b/drivers/thermal/intel_bxt_pmic_thermal.c
@@ -241,7 +241,7 @@ static int pmic_thermal_probe(struct platform_device *pdev)
 	}
 
 	regmap = pmic->regmap;
-	regmap_irq_chip = pmic->irq_chip_data_level2;
+	regmap_irq_chip = pmic->irq_chip_data;
 
 	pmic_irq_count = 0;
 	while ((irq = platform_get_irq(pdev, pmic_irq_count)) != -ENXIO) {
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1658086 — [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-05 21:20 +0200
Subject	[PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
Message-ID	<tP5HI-6Wy-13@gated-at.bofh.it>
In reply to	#1656885

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.

Currently, in this driver all first level IRQs are registered as part of
IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
chip from your driver, all IRQs in that chip will masked and can only be
enabled if that IRQ is requested using request_irq() call. This is the
default Linux IRQ behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level IRQ and not explicitly
unmask the first level IRQ, then in essence the second level IRQ will
still be disabled. For example, if TMU device driver request wake_alarm
IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
Linux IRQ model,  wake_alarm IRQ will still be disabled. So the proper
solution to fix this issue is to use the chained IRQ chip concept. We
should chain all the second level chip IRQs to the corresponding first
level IRQ. To do this, we need to create separate IRQ chips for every
group of second level IRQs.

In case of TMU, when adding second level IRQ chip, instead of using PMIC
IRQ we should use the corresponding first level IRQ. So the following
code will change from

ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)

to,

virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);

ret = regmap_add_irq_chip(pmic->regmap, virq, ...)

In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
to get the USBC virtual IRQ number.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 168 ++++++++++++++++++++++++++++++-------
 drivers/usb/typec/typec_wcove.c    |   2 +-
 include/linux/mfd/intel_soc_pmic.h |   5 +-
 3 files changed, 143 insertions(+), 32 deletions(-)

Changes since v1:
 * Rebased on top of dev_* cleanup patch.
 * Fixed style & grammer issues reported by Lee Jones

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v4:
 * Merged typec driver fix to this patch to prevent branch bisect issue.

Changes since v5:
 * Changed irq->IRQ and pmic -> PMIC.
 * Rearranged tmu related changes to make the patch more readable.
 * Modfied the virq request failure message to include chip name and pirq.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index feeda6e..15bc052 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -82,20 +82,28 @@ enum bxtwc_irqs {
 	BXTWC_PWRBTN_IRQ,
 };
 
-enum bxtwc_irqs_level2 {
-	/* Level 2 */
+enum bxtwc_irqs_bcu {
 	BXTWC_BCU_IRQ = 0,
-	BXTWC_ADC_IRQ,
-	BXTWC_USBC_IRQ,
+};
+
+enum bxtwc_irqs_adc {
+	BXTWC_ADC_IRQ = 0,
+};
+
+enum bxtwc_irqs_chgr {
+	BXTWC_USBC_IRQ = 0,
 	BXTWC_CHGR0_IRQ,
 	BXTWC_CHGR1_IRQ,
-	BXTWC_CRIT_IRQ,
 };
 
 enum bxtwc_irqs_tmu {
 	BXTWC_TMU_IRQ = 0,
 };
 
+enum bxtwc_irqs_crit {
+	BXTWC_CRIT_IRQ = 0,
+};
+
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
 	REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
 	REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
@@ -108,19 +116,28 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
+static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
 	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
-	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
-	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
+	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
+	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
+	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
 	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
 };
 
+static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
+	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
+};
+
 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 	.name = "bxtwc_irq_chip",
 	.status_base = BXTWC_IRQLVL1,
@@ -130,15 +147,6 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 	.num_regs = 2,
 };
 
-static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
-	.name = "bxtwc_irq_chip_level2",
-	.status_base = BXTWC_BCUIRQ,
-	.mask_base = BXTWC_MBCUIRQ,
-	.irqs = bxtwc_regmap_irqs_level2,
-	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
-	.num_regs = 10,
-};
-
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 	.name = "bxtwc_irq_chip_tmu",
 	.status_base = BXTWC_TMUIRQ,
@@ -148,6 +156,42 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 	.num_regs = 1,
 };
 
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
+	.name = "bxtwc_irq_chip_bcu",
+	.status_base = BXTWC_BCUIRQ,
+	.mask_base = BXTWC_MBCUIRQ,
+	.irqs = bxtwc_regmap_irqs_bcu,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
+	.num_regs = 1,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
+	.name = "bxtwc_irq_chip_adc",
+	.status_base = BXTWC_ADCIRQ,
+	.mask_base = BXTWC_MADCIRQ,
+	.irqs = bxtwc_regmap_irqs_adc,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
+	.num_regs = 1,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
+	.name = "bxtwc_irq_chip_chgr",
+	.status_base = BXTWC_CHGR0IRQ,
+	.mask_base = BXTWC_MCHGR0IRQ,
+	.irqs = bxtwc_regmap_irqs_chgr,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
+	.num_regs = 2,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
+	.name = "bxtwc_irq_chip_crit",
+	.status_base = BXTWC_CRITIRQ,
+	.mask_base = BXTWC_MCRITIRQ,
+	.irqs = bxtwc_regmap_irqs_crit,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
+	.num_regs = 1,
+};
+
 static struct resource gpio_resources[] = {
 	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 };
@@ -357,6 +401,26 @@ static const struct regmap_config bxtwc_regmap_config = {
 	.reg_read = regmap_ipc_byte_reg_read,
 };
 
+static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
+				struct regmap_irq_chip_data *pdata,
+				int pirq, int irq_flags,
+				const struct regmap_irq_chip *chip,
+				struct regmap_irq_chip_data **data)
+{
+	int irq;
+
+	irq = regmap_irq_get_virq(pdata, pirq);
+	if (irq < 0) {
+		dev_err(pmic->dev,
+			"Failed to get parent vIRQ(%d) for chip %s, ret:%d\n",
+			pirq, chip->name, irq);
+		return irq;
+	}
+
+	return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
+					0, chip, data);
+}
+
 static int bxtwc_probe(struct platform_device *pdev)
 {
 	int ret;
@@ -408,21 +472,65 @@ static int bxtwc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
-				       IRQF_ONESHOT | IRQF_SHARED,
-				       0, &bxtwc_regmap_irq_chip_level2,
-				       &pmic->irq_chip_data_level2);
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_TMU_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_tmu,
+					 &pmic->irq_chip_data_tmu);
 	if (ret) {
-		dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
+		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
 		return ret;
 	}
 
-	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
-				       IRQF_ONESHOT | IRQF_SHARED,
-				       0, &bxtwc_regmap_irq_chip_tmu,
-				       &pmic->irq_chip_data_tmu);
+	/* Add chained IRQ handler for BCU IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_BCU_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_bcu,
+					 &pmic->irq_chip_data_bcu);
+
+
 	if (ret) {
-		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
+		dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
+		return ret;
+	}
+
+	/* Add chained IRQ handler for ADC IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_ADC_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_adc,
+					 &pmic->irq_chip_data_adc);
+
+
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
+		return ret;
+	}
+
+	/* Add chained IRQ handler for CHGR IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_CHGR_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_chgr,
+					 &pmic->irq_chip_data_chgr);
+
+
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
+		return ret;
+	}
+
+	/* Add chained IRQ handler for CRIT IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_CRIT_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_crit,
+					 &pmic->irq_chip_data_crit);
+
+
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
 		return ret;
 	}
 
diff --git a/drivers/usb/typec/typec_wcove.c b/drivers/usb/typec/typec_wcove.c
index d5a7b21..00a4bd2 100644
--- a/drivers/usb/typec/typec_wcove.c
+++ b/drivers/usb/typec/typec_wcove.c
@@ -303,7 +303,7 @@ static int wcove_typec_probe(struct platform_device *pdev)
 	wcove->dev = &pdev->dev;
 	wcove->regmap = pmic->regmap;
 
-	ret = regmap_irq_get_virq(pmic->irq_chip_data_level2,
+	ret = regmap_irq_get_virq(pmic->irq_chip_data_chgr,
 				  platform_get_irq(pdev, 0));
 	if (ret < 0)
 		return ret;
diff --git a/include/linux/mfd/intel_soc_pmic.h b/include/linux/mfd/intel_soc_pmic.h
index 956caa0..5aacdb0 100644
--- a/include/linux/mfd/intel_soc_pmic.h
+++ b/include/linux/mfd/intel_soc_pmic.h
@@ -25,8 +25,11 @@ struct intel_soc_pmic {
 	int irq;
 	struct regmap *regmap;
 	struct regmap_irq_chip_data *irq_chip_data;
-	struct regmap_irq_chip_data *irq_chip_data_level2;
 	struct regmap_irq_chip_data *irq_chip_data_tmu;
+	struct regmap_irq_chip_data *irq_chip_data_bcu;
+	struct regmap_irq_chip_data *irq_chip_data_adc;
+	struct regmap_irq_chip_data *irq_chip_data_chgr;
+	struct regmap_irq_chip_data *irq_chip_data_crit;
 	struct device *dev;
 };
 
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1658540 — Re: [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

From	Heikki Krogerus <heikki.krogerus@linux.intel.com>
Date	2017-06-06 11:40 +0200
Subject	Re: [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
Message-ID	<tPj7Z-6SP-27@gated-at.bofh.it>
In reply to	#1658086

On Mon, Jun 05, 2017 at 12:08:05PM -0700, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> 
> Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
> At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
> CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
> to mask/unmask individual interrupts belong each of this domain. For
> example, in case of TMU, at first level we have TMU interrupt domain,
> and at second level we have two interrupts, wake alarm, system alarm that
> belong to the TMU interrupt domain.
> 
> Currently, in this driver all first level IRQs are registered as part of
> IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
> chip from your driver, all IRQs in that chip will masked and can only be
> enabled if that IRQ is requested using request_irq() call. This is the
> default Linux IRQ behavior model. And whenever a dependent device that
> belongs to PMIC requests only the second level IRQ and not explicitly
> unmask the first level IRQ, then in essence the second level IRQ will
> still be disabled. For example, if TMU device driver request wake_alarm
> IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
> Linux IRQ model,  wake_alarm IRQ will still be disabled. So the proper
> solution to fix this issue is to use the chained IRQ chip concept. We
> should chain all the second level chip IRQs to the corresponding first
> level IRQ. To do this, we need to create separate IRQ chips for every
> group of second level IRQs.
> 
> In case of TMU, when adding second level IRQ chip, instead of using PMIC
> IRQ we should use the corresponding first level IRQ. So the following
> code will change from
> 
> ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)
> 
> to,
> 
> virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);
> 
> ret = regmap_add_irq_chip(pmic->regmap, virq, ...)
> 
> In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
> charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
> to get the USBC virtual IRQ number.
> 
> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>

For the typec_wcove.c part:

Revieved-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>


Thanks,

-- 
heikki

[toc] | [prev] | [next] | [standalone]

#1658088 — [PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-05 21:20 +0200
Subject	[PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
Message-ID	<tP5HI-6Wy-19@gated-at.bofh.it>
In reply to	#1656885

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of IRQs as 12 instead of actual
value of 1.

This patch fixes this issue by creating new enum of tmu IRQs and
resetting its starting index to 0.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Changes since v1: 
 * Removed code from commit message.

Changes since v2: 
 * Rebased on top of latest release.

Changes sinve v3:
 * Rebased on top of latest release.

Changes sinve v5:
 * Changed irq to IRQ.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 8c3cbf6..7cbaf1e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
 	BXTWC_GPIO0_IRQ,
 	BXTWC_GPIO1_IRQ,
 	BXTWC_CRIT_IRQ,
-	BXTWC_TMU_IRQ,
+};
+
+enum bxtwc_irqs_tmu {
+	BXTWC_TMU_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1658089 — [PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-05 21:20 +0200
Subject	[PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
Message-ID	<tP5HI-6Wy-21@gated-at.bofh.it>
In reply to	#1656885

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Cleanup the resource allocation/free code in probe function by using
devm_* calls.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 54 +++++++++++++-------------------------
 1 file changed, 18 insertions(+), 36 deletions(-)

Changes since v1:
 * None

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v5:
 * None

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index af11c43..feeda6e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -399,45 +399,44 @@ static int bxtwc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
-				  IRQF_ONESHOT | IRQF_SHARED,
-				  0, &bxtwc_regmap_irq_chip,
-				  &pmic->irq_chip_data);
+	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
+				       IRQF_ONESHOT | IRQF_SHARED,
+				       0, &bxtwc_regmap_irq_chip,
+				       &pmic->irq_chip_data);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to add IRQ chip\n");
 		return ret;
 	}
 
-	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
-				  IRQF_ONESHOT | IRQF_SHARED,
-				  0, &bxtwc_regmap_irq_chip_level2,
-				  &pmic->irq_chip_data_level2);
+	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
+				       IRQF_ONESHOT | IRQF_SHARED,
+				       0, &bxtwc_regmap_irq_chip_level2,
+				       &pmic->irq_chip_data_level2);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
-		goto err_irq_chip_level2;
+		return ret;
 	}
 
-	ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
-				  IRQF_ONESHOT | IRQF_SHARED,
-				  0, &bxtwc_regmap_irq_chip_tmu,
-				  &pmic->irq_chip_data_tmu);
+	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
+				       IRQF_ONESHOT | IRQF_SHARED,
+				       0, &bxtwc_regmap_irq_chip_tmu,
+				       &pmic->irq_chip_data_tmu);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
-		goto err_irq_chip_tmu;
+		return ret;
 	}
 
-	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
-			      ARRAY_SIZE(bxt_wc_dev), NULL, 0,
-			      NULL);
+	ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
+				   ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to add devices\n");
-		goto err_mfd;
+		return ret;
 	}
 
 	ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
-		goto err_sysfs;
+		return ret;
 	}
 
 	/*
@@ -451,28 +450,11 @@ static int bxtwc_probe(struct platform_device *pdev)
 				BXTWC_MIRQLVL1_MCHGR, 0);
 
 	return 0;
-
-err_sysfs:
-	mfd_remove_devices(&pdev->dev);
-err_mfd:
-	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
-err_irq_chip_tmu:
-	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-err_irq_chip_level2:
-	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-
-	return ret;
 }
 
 static int bxtwc_remove(struct platform_device *pdev)
 {
-	struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
-
 	sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
-	mfd_remove_devices(&pdev->dev);
-	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
-	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
-	regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_tmu);
 
 	return 0;
 }
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1658090 — [PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-05 21:20 +0200
Subject	[PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
Message-ID	<tP5HI-6Wy-23@gated-at.bofh.it>
In reply to	#1656885

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Currently all PMIC GPIO domain IRQs are consumed by the same
device(bxt_wcove_gpio), so there is no need to export them as
separate interrupts. We can just export only the first level
GPIO IRQ(BXTWC_GPIO_LVL1_IRQ) as an IRQ resource and let the
GPIO device driver(bxt_wcove_gpio) handle the GPIO sub domain
IRQs based on status value of GPIO level2 interrupt status
register. Also, just using only the first level IRQ will eliminate
the bug involved in requesting only the second level IRQ and not
explicitly enable the first level IRQ. For more info on this
issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

This patch also makes relevant change in Whiskey cove GPIO driver to
use only first level PMIC GPIO IRQ.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/gpio/gpio-wcove.c          | 14 +++++++++++++-
 drivers/mfd/intel_soc_pmic_bxtwc.c |  7 +------
 2 files changed, 14 insertions(+), 7 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v5:
 * Squashed gpio driver patch.
 * Changes irq -> IRQ.

diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20..bba7704 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 	if (!wg)
 		return -ENOMEM;
 
-	wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+	wg->regmap_irq_chip = pmic->irq_chip_data;
 
 	platform_set_drvdata(pdev, wg);
 
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 
 	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
 
+	/* Enable GPIO0 interrupts */
+	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+				 0x00);
+	if (ret)
+		return ret;
+
+	/* Enable GPIO1 interrupts */
+	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+				 0x00);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7c1ed27..af11c43 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -89,8 +89,6 @@ enum bxtwc_irqs_level2 {
 	BXTWC_USBC_IRQ,
 	BXTWC_CHGR0_IRQ,
 	BXTWC_CHGR1_IRQ,
-	BXTWC_GPIO0_IRQ,
-	BXTWC_GPIO1_IRQ,
 	BXTWC_CRIT_IRQ,
 };
 
@@ -116,8 +114,6 @@ static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
 	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
 	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
 	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
-	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
 	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
@@ -153,8 +149,7 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 };
 
 static struct resource gpio_resources[] = {
-	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
-	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
+	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 };
 
 static struct resource adc_resources[] = {
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1658091 — [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-05 21:20 +0200
Subject	[PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support
Message-ID	<tP5HI-6Wy-25@gated-at.bofh.it>
In reply to	#1656885

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Following patch set adds chained IRQ support to WCOVE PMIC driver.

Changes since v3:
 * Added fix for typec wcove driver.

Changes since v4:
 * Squashed following two commits, to keep the patch set bisectable.
   usb: typec: typec_wcove: Use charger irq chip to get usbc virq
   mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

Changes since v5:
* Changed irq->IRQ, pmic->PMIC in all commit messages.
* Squashed following two thermal driver related commits.
  mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
  thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
* Squashed following two GPIO driver related commits.
  mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
  gpio: gpio-wcove: Use first level PMIC GPIO irq

Kuppuswamy Sathyanarayanan (6):
  mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
  mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
  mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
  mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
  mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
  platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask

 drivers/gpio/gpio-wcove.c                |  14 +-
 drivers/mfd/intel_soc_pmic_bxtwc.c       | 232 +++++++++++++++++++++----------
 drivers/platform/x86/intel_bxtwc_tmu.c   |   4 -
 drivers/thermal/intel_bxt_pmic_thermal.c |   2 +-
 drivers/usb/typec/typec_wcove.c          |   2 +-
 include/linux/mfd/intel_soc_pmic.h       |   5 +-
 6 files changed, 175 insertions(+), 84 deletions(-)

-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1658544 — Re: [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

From	Andy Shevchenko <andy.shevchenko@gmail.com>
Date	2017-06-06 11:40 +0200
Subject	Re: [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support
Message-ID	<tPj7Z-6SP-41@gated-at.bofh.it>
In reply to	#1658091

On Mon, Jun 5, 2017 at 10:08 PM,
<sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>
> Following patch set adds chained IRQ support to WCOVE PMIC driver.

Assuming it has been tested,

Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

to the patches which do not have it yet.

> Changes since v3:
>  * Added fix for typec wcove driver.
>
> Changes since v4:
>  * Squashed following two commits, to keep the patch set bisectable.
>    usb: typec: typec_wcove: Use charger irq chip to get usbc virq
>    mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips
>
> Changes since v5:
> * Changed irq->IRQ, pmic->PMIC in all commit messages.
> * Squashed following two thermal driver related commits.
>   mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
>   thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
> * Squashed following two GPIO driver related commits.
>   mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
>   gpio: gpio-wcove: Use first level PMIC GPIO irq
>
> Kuppuswamy Sathyanarayanan (6):
>   mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
>   mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs
>   mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device
>   mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
>   mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
>   platform/x86: intel_bxtwc_tmu: Remove first level IRQ unmask
>
>  drivers/gpio/gpio-wcove.c                |  14 +-
>  drivers/mfd/intel_soc_pmic_bxtwc.c       | 232 +++++++++++++++++++++----------
>  drivers/platform/x86/intel_bxtwc_tmu.c   |   4 -
>  drivers/thermal/intel_bxt_pmic_thermal.c |   2 +-
>  drivers/usb/typec/typec_wcove.c          |   2 +-
>  include/linux/mfd/intel_soc_pmic.h       |   5 +-
>  6 files changed, 175 insertions(+), 84 deletions(-)
>
> --
> 2.7.4
>



-- 
With Best Regards,
Andy Shevchenko

[toc] | [prev] | [next] | [standalone]

#1654700 — [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-01 00:50 +0200
Subject	[PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support
Message-ID	<tNkBc-2ET-27@gated-at.bofh.it>
In reply to	#1653895

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Following patch set adds chained IRQ support to WCOVE PMIC driver.

Changes since v3:
 * Added fix for typec wcove driver.

Changes since v4:
 * Squashed following two commits, to keep the patch set bisectable.
   usb: typec: typec_wcove: Use charger irq chip to get usbc virq
   mfd: intel_soc_pmic_bxtwc: use chained irqs for second level irq chips

Kuppuswamy Sathyanarayanan (8):
  mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
  mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
  thermal: intel_bxt_pmic_thermal: Use first level PMIC thermal irq
  mfd: intel_soc_pmic_bxtwc: Remove second level irq for gpio device
  gpio: gpio-wcove: Use first level PMIC GPIO irq
  mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe
  mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips
  platform/x86: intel_bxtwc_tmu: Remove first level irq unmask

 drivers/gpio/gpio-wcove.c                |  14 +-
 drivers/mfd/intel_soc_pmic_bxtwc.c       | 234 ++++++++++++++++++++-----------
 drivers/platform/x86/intel_bxtwc_tmu.c   |   4 -
 drivers/thermal/intel_bxt_pmic_thermal.c |   2 +-
 drivers/usb/typec/typec_wcove.c          |   2 +-
 include/linux/mfd/intel_soc_pmic.h       |   5 +-
 6 files changed, 175 insertions(+), 86 deletions(-)

-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1656799 — Re: [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

From	Andy Shevchenko <andy.shevchenko@gmail.com>
Date	2017-06-03 15:30 +0200
Subject	Re: [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support
Message-ID	<tOhhU-7wJ-5@gated-at.bofh.it>
In reply to	#1654700

On Thu, Jun 1, 2017 at 1:37 AM,
<sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>
> Following patch set adds chained IRQ support to WCOVE PMIC driver.

I commented some patches, the rest looks okay.
Please, address and send new version.

-- 
With Best Regards,
Andy Shevchenko

[toc] | [prev] | [next] | [standalone]

#1654701 — [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-01 00:50 +0200
Subject	[PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips
Message-ID	<tNkBc-2ET-31@gated-at.bofh.it>
In reply to	#1653895

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.

Currently, in this driver all first level irqs are registered as part of
irq chip(bxtwc_regmap_irq_chip). By default, after you register the irq
chip from your driver, all irqs in that chip will masked and can only be
enabled if that irq is requested using request_irq call. This is the
default Linux irq behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level irq and not explicitly
unmask the first level irq, then in essence the second level irq will
still be disabled. For example, if TMU device driver request wake_alarm
irq and not explicitly unmask TMU level 1 irq then according to the default
Linux irq model,  wake_alarm irq will still be disabled. So the proper
solution to fix this issue is to use the chained irq chip concept. We
should chain all the second level chip irqs to the corresponding first
level irq. To do this, we need to create separate irq chips for every
group of second level irqs.

In case of TMU, when adding second level irq chip, instead of using pmic
irq we should use the corresponding first level irq. So the following
code will change from

ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)

to,

virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);

ret = regmap_add_irq_chip(pmic->regmap, virq, ...)

In case of typec wcove driver, Since USBC IRQ is moved under charger level2
irq chip. We should use charger irq chip(irq_chip_data_chgr) to get the USBC
virtual IRQ number.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 174 +++++++++++++++++++++++++++++--------
 drivers/usb/typec/typec_wcove.c    |   2 +-
 include/linux/mfd/intel_soc_pmic.h |   5 +-
 3 files changed, 145 insertions(+), 36 deletions(-)

Changes since v1:
 * Rebased on top of dev_* cleanup patch.
 * Fixed style & grammer issues reported by Lee Jones

Changes since v2:
 * Rebased on top of latest release.

Changes since v3:
 * None

Changes since v4:
 * Merged typec driver fix to this patch to prevent branch bisect issue.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index feeda6e..bd78bef 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -82,18 +82,26 @@ enum bxtwc_irqs {
 	BXTWC_PWRBTN_IRQ,
 };
 
-enum bxtwc_irqs_level2 {
-	/* Level 2 */
+enum bxtwc_irqs_tmu {
+	BXTWC_TMU_IRQ = 0,
+};
+
+enum bxtwc_irqs_bcu {
 	BXTWC_BCU_IRQ = 0,
-	BXTWC_ADC_IRQ,
-	BXTWC_USBC_IRQ,
+};
+
+enum bxtwc_irqs_adc {
+	BXTWC_ADC_IRQ = 0,
+};
+
+enum bxtwc_irqs_chgr {
+	BXTWC_USBC_IRQ = 0,
 	BXTWC_CHGR0_IRQ,
 	BXTWC_CHGR1_IRQ,
-	BXTWC_CRIT_IRQ,
 };
 
-enum bxtwc_irqs_tmu {
-	BXTWC_TMU_IRQ = 0,
+enum bxtwc_irqs_crit {
+	BXTWC_CRIT_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
@@ -108,17 +116,26 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 	REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
+static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
+	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
 	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
-	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
-	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
-static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
-	REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
+static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
+	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
+	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
+	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f),
+};
+
+static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
+	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03),
 };
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
@@ -130,15 +147,6 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 	.num_regs = 2,
 };
 
-static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
-	.name = "bxtwc_irq_chip_level2",
-	.status_base = BXTWC_BCUIRQ,
-	.mask_base = BXTWC_MBCUIRQ,
-	.irqs = bxtwc_regmap_irqs_level2,
-	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
-	.num_regs = 10,
-};
-
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 	.name = "bxtwc_irq_chip_tmu",
 	.status_base = BXTWC_TMUIRQ,
@@ -148,6 +156,42 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {
 	.num_regs = 1,
 };
 
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {
+	.name = "bxtwc_irq_chip_bcu",
+	.status_base = BXTWC_BCUIRQ,
+	.mask_base = BXTWC_MBCUIRQ,
+	.irqs = bxtwc_regmap_irqs_bcu,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),
+	.num_regs = 1,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {
+	.name = "bxtwc_irq_chip_adc",
+	.status_base = BXTWC_ADCIRQ,
+	.mask_base = BXTWC_MADCIRQ,
+	.irqs = bxtwc_regmap_irqs_adc,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),
+	.num_regs = 1,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {
+	.name = "bxtwc_irq_chip_chgr",
+	.status_base = BXTWC_CHGR0IRQ,
+	.mask_base = BXTWC_MCHGR0IRQ,
+	.irqs = bxtwc_regmap_irqs_chgr,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),
+	.num_regs = 2,
+};
+
+static struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {
+	.name = "bxtwc_irq_chip_crit",
+	.status_base = BXTWC_CRITIRQ,
+	.mask_base = BXTWC_MCRITIRQ,
+	.irqs = bxtwc_regmap_irqs_crit,
+	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),
+	.num_regs = 1,
+};
+
 static struct resource gpio_resources[] = {
 	DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),
 };
@@ -357,6 +401,24 @@ static const struct regmap_config bxtwc_regmap_config = {
 	.reg_read = regmap_ipc_byte_reg_read,
 };
 
+static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
+				struct regmap_irq_chip_data *pdata,
+				int pirq, int irq_flags,
+				const struct regmap_irq_chip *chip,
+				struct regmap_irq_chip_data **data)
+{
+	int irq;
+
+	irq = regmap_irq_get_virq(pdata, pirq);
+	if (irq < 0) {
+		dev_err(pmic->dev, "failed to get virtual interrupt:%d\n", irq);
+		return irq;
+	}
+
+	return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
+					0, chip, data);
+}
+
 static int bxtwc_probe(struct platform_device *pdev)
 {
 	int ret;
@@ -408,21 +470,65 @@ static int bxtwc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
-				       IRQF_ONESHOT | IRQF_SHARED,
-				       0, &bxtwc_regmap_irq_chip_level2,
-				       &pmic->irq_chip_data_level2);
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_TMU_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_tmu,
+					 &pmic->irq_chip_data_tmu);
 	if (ret) {
-		dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
+		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
 		return ret;
 	}
 
-	ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq,
-				       IRQF_ONESHOT | IRQF_SHARED,
-				       0, &bxtwc_regmap_irq_chip_tmu,
-				       &pmic->irq_chip_data_tmu);
+	/* Add chained IRQ handler for BCU IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_BCU_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_bcu,
+					 &pmic->irq_chip_data_bcu);
+
+
 	if (ret) {
-		dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n");
+		dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
+		return ret;
+	}
+
+	/* Add chained IRQ handler for ADC IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_ADC_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_adc,
+					 &pmic->irq_chip_data_adc);
+
+
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
+		return ret;
+	}
+
+	/* Add chained IRQ handler for CHGR IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_CHGR_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_chgr,
+					 &pmic->irq_chip_data_chgr);
+
+
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
+		return ret;
+	}
+
+	/* Add chained IRQ handler for CRIT IRQs */
+	ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
+					 BXTWC_CRIT_LVL1_IRQ,
+					 IRQF_ONESHOT,
+					 &bxtwc_regmap_irq_chip_crit,
+					 &pmic->irq_chip_data_crit);
+
+
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n");
 		return ret;
 	}
 
diff --git a/drivers/usb/typec/typec_wcove.c b/drivers/usb/typec/typec_wcove.c
index d5a7b21..00a4bd2 100644
--- a/drivers/usb/typec/typec_wcove.c
+++ b/drivers/usb/typec/typec_wcove.c
@@ -303,7 +303,7 @@ static int wcove_typec_probe(struct platform_device *pdev)
 	wcove->dev = &pdev->dev;
 	wcove->regmap = pmic->regmap;
 
-	ret = regmap_irq_get_virq(pmic->irq_chip_data_level2,
+	ret = regmap_irq_get_virq(pmic->irq_chip_data_chgr,
 				  platform_get_irq(pdev, 0));
 	if (ret < 0)
 		return ret;
diff --git a/include/linux/mfd/intel_soc_pmic.h b/include/linux/mfd/intel_soc_pmic.h
index 956caa0..5aacdb0 100644
--- a/include/linux/mfd/intel_soc_pmic.h
+++ b/include/linux/mfd/intel_soc_pmic.h
@@ -25,8 +25,11 @@ struct intel_soc_pmic {
 	int irq;
 	struct regmap *regmap;
 	struct regmap_irq_chip_data *irq_chip_data;
-	struct regmap_irq_chip_data *irq_chip_data_level2;
 	struct regmap_irq_chip_data *irq_chip_data_tmu;
+	struct regmap_irq_chip_data *irq_chip_data_bcu;
+	struct regmap_irq_chip_data *irq_chip_data_adc;
+	struct regmap_irq_chip_data *irq_chip_data_chgr;
+	struct regmap_irq_chip_data *irq_chip_data_crit;
 	struct device *dev;
 };
 
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1656798 — Re: [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips

From	Andy Shevchenko <andy.shevchenko@gmail.com>
Date	2017-06-03 15:30 +0200
Subject	Re: [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips
Message-ID	<tOhhT-7wJ-1@gated-at.bofh.it>
In reply to	#1654701

On Thu, Jun 1, 2017 at 1:37 AM,
<sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>
> Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
> At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
> CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
> to mask/unmask individual interrupts belong each of this domain. For
> example, in case of TMU, at first level we have TMU interrupt domain,
> and at second level we have two interrupts, wake alarm, system alarm that
> belong to the TMU interrupt domain.
>
> Currently, in this driver all first level irqs are registered as part of
> irq chip(bxtwc_regmap_irq_chip). By default, after you register the irq
> chip from your driver, all irqs in that chip will masked and can only be
> enabled if that irq is requested using request_irq call. This is the
> default Linux irq behavior model. And whenever a dependent device that
> belongs to PMIC requests only the second level irq and not explicitly
> unmask the first level irq, then in essence the second level irq will
> still be disabled. For example, if TMU device driver request wake_alarm
> irq and not explicitly unmask TMU level 1 irq then according to the default
> Linux irq model,  wake_alarm irq will still be disabled. So the proper
> solution to fix this issue is to use the chained irq chip concept. We
> should chain all the second level chip irqs to the corresponding first
> level irq. To do this, we need to create separate irq chips for every
> group of second level irqs.
>
> In case of TMU, when adding second level irq chip, instead of using pmic
> irq we should use the corresponding first level irq. So the following
> code will change from

pmic -> PMIC
irq -> IRQ
irqs -> IRQs

These do apply to entire commit message.

>
> ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)
>
> to,
>
> virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);
>
> ret = regmap_add_irq_chip(pmic->regmap, virq, ...)
>
> In case of typec wcove driver, Since USBC IRQ is moved under charger level2
> irq chip. We should use charger irq chip(irq_chip_data_chgr) to get the USBC
> virtual IRQ number.

typec wcove -> Whiskey Cove Type-C

> +enum bxtwc_irqs_tmu {
> +       BXTWC_TMU_IRQ = 0,
> +};

> -enum bxtwc_irqs_tmu {
> -       BXTWC_TMU_IRQ = 0,

Leave it on the same place it will make patch a bit more cleaner.

> +static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
> +       REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),
> +};

> -static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
> -       REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06),

Ditto.

> +static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
> +                               struct regmap_irq_chip_data *pdata,
> +                               int pirq, int irq_flags,
> +                               const struct regmap_irq_chip *chip,
> +                               struct regmap_irq_chip_data **data)
> +{
> +       int irq;
> +
> +       irq = regmap_irq_get_virq(pdata, pirq);
> +       if (irq < 0) {
> +               dev_err(pmic->dev, "failed to get virtual interrupt:%d\n", irq);

Follow below pattern, i.e. "Failed to ..."

Moreover, it would be useful to see for which interrupt we are trying
to get a virtual one.
chip->name + pirq I guess would give us a thing.

> +               return irq;
> +       }
> +
> +       return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
> +                                       0, chip, data);
> +}

-- 
With Best Regards,
Andy Shevchenko

[toc] | [prev] | [next] | [standalone]

#1654702 — [PATCH v5 2/8] mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-01 00:50 +0200
Subject	[PATCH v5 2/8] mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs
Message-ID	<tNkBc-2ET-29@gated-at.bofh.it>
In reply to	#1653895

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Since all second level thermal irqs are consumed by the same
device(bxt_wcove_thermal), there is no need to expose them as separate
interrupts. We can just export only the first level irqs for thermal and
let the device(bxt_wcove_thermal) driver handle the second level irqs
based on thermal interrupt status register. Also, just using only the
first level irq will eliminate the bug involved in requesting only the
second level irq and not explicitly enable the first level irq. For
more info on this issue please read the details at,

https://lkml.org/lkml/2017/2/27/148

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 32 ++++++++++++--------------------
 1 file changed, 12 insertions(+), 20 deletions(-)

Changes since v1:
 * None

Changes since v2: 
 * Rebased on top of latest release.

Changes since v3:
 * Rebased on top of latest release.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 7cbaf1e..7c1ed27 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -84,10 +84,7 @@ enum bxtwc_irqs {
 
 enum bxtwc_irqs_level2 {
 	/* Level 2 */
-	BXTWC_THRM0_IRQ = 0,
-	BXTWC_THRM1_IRQ,
-	BXTWC_THRM2_IRQ,
-	BXTWC_BCU_IRQ,
+	BXTWC_BCU_IRQ = 0,
 	BXTWC_ADC_IRQ,
 	BXTWC_USBC_IRQ,
 	BXTWC_CHGR0_IRQ,
@@ -114,17 +111,14 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
-	REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
-	REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
-	REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
-	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
-	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 5, BIT(5)),
-	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
-	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
-	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
-	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
+	REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 1, 0xff),
+	REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 2, BIT(5)),
+	REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 2, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 3, 0x1f),
+	REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 4, 0xff),
+	REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 5, 0x3f),
+	REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 6, 0x03),
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
@@ -142,8 +136,8 @@ static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
 
 static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
 	.name = "bxtwc_irq_chip_level2",
-	.status_base = BXTWC_THRM0IRQ,
-	.mask_base = BXTWC_MTHRM0IRQ,
+	.status_base = BXTWC_BCUIRQ,
+	.mask_base = BXTWC_MBCUIRQ,
 	.irqs = bxtwc_regmap_irqs_level2,
 	.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
 	.num_regs = 10,
@@ -177,9 +171,7 @@ static struct resource charger_resources[] = {
 };
 
 static struct resource thermal_resources[] = {
-	DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
-	DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
-	DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
+	DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),
 };
 
 static struct resource bcu_resources[] = {
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1654706 — [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-01 00:50 +0200
Subject	[PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq
Message-ID	<tNkBc-2ET-37@gated-at.bofh.it>
In reply to	#1653895

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

PMIC mfd driver only exports first level irq for GPIO device.
But currently we are reading the irqs from the second level irq
chip, So this patch fixes this issue by adding support to use
first level PMIC GPIO irq.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/gpio/gpio-wcove.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

Changes since v1:
 * used correct mask for GPIO0 and GPIO1 interrupts

Changes since v2: 
 * Rebased on top of latest release.
 * Removed IRQ0 and IRQ1 mask defines.

Changes since v3:
 * None

diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
index 7b1bc20..bba7704 100644
--- a/drivers/gpio/gpio-wcove.c
+++ b/drivers/gpio/gpio-wcove.c
@@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 	if (!wg)
 		return -ENOMEM;
 
-	wg->regmap_irq_chip = pmic->irq_chip_data_level2;
+	wg->regmap_irq_chip = pmic->irq_chip_data;
 
 	platform_set_drvdata(pdev, wg);
 
@@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
 
 	gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
 
+	/* Enable GPIO0 interrupts */
+	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
+				 0x00);
+	if (ret)
+		return ret;
+
+	/* Enable GPIO1 interrupts */
+	ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
+				 0x00);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
-- 
2.7.4

[toc] | [prev] | [next] | [standalone]

#1656797 — Re: [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq

From	Andy Shevchenko <andy.shevchenko@gmail.com>
Date	2017-06-03 15:10 +0200
Subject	Re: [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq
Message-ID	<tOgYy-7qy-23@gated-at.bofh.it>
In reply to	#1654706

On Thu, Jun 1, 2017 at 1:37 AM,
<sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>
> PMIC mfd driver only exports first level irq for GPIO device.
> But currently we are reading the irqs from the second level irq
> chip, So this patch fixes this issue by adding support to use
> first level PMIC GPIO irq.
>

Shouldn't be this squashed to patch 4?

> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  drivers/gpio/gpio-wcove.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>
> Changes since v1:
>  * used correct mask for GPIO0 and GPIO1 interrupts
>
> Changes since v2:
>  * Rebased on top of latest release.
>  * Removed IRQ0 and IRQ1 mask defines.
>
> Changes since v3:
>  * None
>
> diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
> index 7b1bc20..bba7704 100644
> --- a/drivers/gpio/gpio-wcove.c
> +++ b/drivers/gpio/gpio-wcove.c
> @@ -401,7 +401,7 @@ static int wcove_gpio_probe(struct platform_device *pdev)
>         if (!wg)
>                 return -ENOMEM;
>
> -       wg->regmap_irq_chip = pmic->irq_chip_data_level2;
> +       wg->regmap_irq_chip = pmic->irq_chip_data;
>
>         platform_set_drvdata(pdev, wg);
>
> @@ -449,6 +449,18 @@ static int wcove_gpio_probe(struct platform_device *pdev)
>
>         gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq);
>
> +       /* Enable GPIO0 interrupts */
> +       ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK,
> +                                0x00);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable GPIO1 interrupts */
> +       ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK,
> +                                0x00);
> +       if (ret)
> +               return ret;
> +
>         return 0;
>  }
>
> --
> 2.7.4
>



-- 
With Best Regards,
Andy Shevchenko

[toc] | [prev] | [next] | [standalone]

#1654708 — [PATCH v5 1/8] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

From	sathyanarayanan.kuppuswamy@linux.intel.com
Date	2017-06-01 00:50 +0200
Subject	[PATCH v5 1/8] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index
Message-ID	<tNkBc-2ET-41@gated-at.bofh.it>
In reply to	#1653895

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

TMU interrupts are registered as a separate interrupt chip, and
hence it should start its interrupt index(BXTWC_TMU_IRQ) number
from 0. But currently, BXTWC_TMU_IRQ is defined as part of enum
bxtwc_irqs_level2 and its index value is 11. Since this index
value is used when calculating .num_irqs of regmap_irq_chip_tmu,
it incorrectly reports number of irqs as 12 instead of actual
value of 1.

This patch fixes this issue by creating new enum of tmu irqs and
resetting its starting index to 0.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/intel_soc_pmic_bxtwc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Changes since v1: 
 * Removed code from commit message.

Changes since v2: 
 * Rebased on top of latest release.

Changes sinve v3:
 * Rebased on top of latest release.

diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c
index 8c3cbf6..7cbaf1e 100644
--- a/drivers/mfd/intel_soc_pmic_bxtwc.c
+++ b/drivers/mfd/intel_soc_pmic_bxtwc.c
@@ -95,7 +95,10 @@ enum bxtwc_irqs_level2 {
 	BXTWC_GPIO0_IRQ,
 	BXTWC_GPIO1_IRQ,
 	BXTWC_CRIT_IRQ,
-	BXTWC_TMU_IRQ,
+};
+
+enum bxtwc_irqs_tmu {
+	BXTWC_TMU_IRQ = 0,
 };
 
 static const struct regmap_irq bxtwc_regmap_irqs[] = {
-- 
2.7.4

[toc] | [prev] | [standalone]

Page 2 of 2 — ← Prev page 1 [2]

csiph-web

[GIT PULL] Immutable branch between MFD, GPIO, Thermal and X86 due for the v4.13 merge window

Contents

#1658084 — [PATCH v6 2/6] mfd: intel_soc_pmic_bxtwc: Remove thermal second level IRQs

#1658086 — [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

#1658540 — Re: [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

#1658088 — [PATCH v6 1/6] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index

#1658089 — [PATCH v6 4/6] mfd: intel_soc_pmic_bxtwc: Utilize devm_* functions in driver probe

#1658090 — [PATCH v6 3/6] mfd: intel_soc_pmic_bxtwc: Remove second level IRQ for gpio device

#1658091 — [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

#1658544 — Re: [PATCH v6 0/6] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

#1654700 — [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

#1656799 — Re: [PATCH v5 0/8] mfd: intel_soc_pmic_bxtwc: Add chained IRQ support

#1654701 — [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips

#1656798 — Re: [PATCH v5 7/8] mfd: intel_soc_pmic_bxtwc: Use chained irqs for second level irq chips

#1654702 — [PATCH v5 2/8] mfd: intel_soc_pmic_bxtwc: Remove thermal second level irqs

#1654706 — [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq

#1656797 — Re: [PATCH v5 5/8] gpio: gpio-wcove: Use first level PMIC GPIO irq

#1654708 — [PATCH v5 1/8] mfd: intel_soc_pmic_bxtwc: Fix TMU interrupt index