Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1653759 > unrolled thread

[PATCH 0/2] Add usb nodes on rk322x SoCs and enable usb on rk3229 evb

Started byWilliam Wu <william.wu@rock-chips.com>
First post2017-05-31 03:30 +0200
Last post2017-05-31 03:30 +0200
Articles 5 — 3 participants

Back to article view | Back to linux.kernel

Contents

  [PATCH 0/2] Add usb nodes on rk322x SoCs and enable usb on rk3229 evb William Wu <william.wu@rock-chips.com> - 2017-05-31 03:30 +0200
    [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x William Wu <william.wu@rock-chips.com> - 2017-05-31 03:30 +0200
      Re: [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x Heiko Stuebner <heiko@sntech.de> - 2017-06-01 22:30 +0200
        Re: [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x wlf <wulf@rock-chips.com> - 2017-06-02 03:50 +0200
    [PATCH 2/2] ARM: dts: rockchip: enable usb for rk3229 evb board William Wu <william.wu@rock-chips.com> - 2017-05-31 03:30 +0200

#1653759 — [PATCH 0/2] Add usb nodes on rk322x SoCs and enable usb on rk3229 evb

FromWilliam Wu <william.wu@rock-chips.com>
Date2017-05-31 03:30 +0200
Subject[PATCH 0/2] Add usb nodes on rk322x SoCs and enable usb on rk3229 evb
Message-ID<tN0Ct-6qZ-1@gated-at.bofh.it>
This series adds support for usb on rk322x SoCs.

William Wu (2):
  ARM: dts: rockchip: add usb nodes on rk322x
  ARM: dts: rockchip: enable usb for rk3229 evb board

Tested on rk3229 evb board, and depended on the following
patches and config.
[1] https://patchwork.kernel.org/patch/9732473/
[2] https://patchwork.kernel.org/patch/9732475/
[3] https://patchwork.kernel.org/patch/9732481/
[4] https://patchwork.kernel.org/patch/9732479/  
[5] enable CONFIG_PHY_ROCKCHIP_INNO_USB2

 arch/arm/boot/dts/rk3229-evb.dts |  74 +++++++++++++++++++++
 arch/arm/boot/dts/rk322x.dtsi    | 138 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 211 insertions(+), 1 deletion(-)

-- 
2.0.0

[toc] | [next] | [standalone]

#1653760 — [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x

FromWilliam Wu <william.wu@rock-chips.com>
Date2017-05-31 03:30 +0200
Subject[PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x
Message-ID<tN0Ct-6qZ-5@gated-at.bofh.it>
In reply to#1653759
This patch adds usb otg/host controllers and phys nodes on rk322x.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
 arch/arm/boot/dts/rk322x.dtsi | 138 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 137 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index df57413..d4bfd3c 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -210,8 +210,61 @@
 	};
 
 	grf: syscon@11000000 {
-		compatible = "syscon";
+		compatible = "syscon", "simple-mfd";
 		reg = <0x11000000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy0: usb2-phy@760 {
+			compatible = "rockchip,rk322x-usb2phy";
+			reg = <0x0760 0x0c>;
+			clocks = <&cru SCLK_OTGPHY0>;
+			clock-names = "phyclk";
+			#clock-cells = <0>;
+			clock-output-names = "usb480m_phy0";
+			status = "disabled";
+
+			u2phy0_otg: otg-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid", "otg-id",
+						  "linestate";
+				status = "disabled";
+			};
+
+			u2phy0_host: host-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "disabled";
+			};
+		};
+
+		u2phy1: usb2-phy@800 {
+			compatible = "rockchip,rk322x-usb2phy";
+			reg = <0x0800 0x0c>;
+			clocks = <&cru SCLK_OTGPHY1>;
+			clock-names = "phyclk";
+			#clock-cells = <0>;
+			clock-output-names = "usb480m_phy1";
+			status = "disabled";
+
+			u2phy1_otg: otg-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "disabled";
+			};
+
+			u2phy1_host: host-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "disabled";
+			};
+		};
 	};
 
 	uart0: serial@11010000 {
@@ -467,6 +520,89 @@
 		status = "disabled";
 	};
 
+	usb_otg: usb@30040000 {
+		compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
+			     "snps,dwc2";
+		reg = <0x30040000 0x40000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_OTG>;
+		clock-names = "otg";
+		dr_mode = "otg";
+		g-np-tx-fifo-size = <16>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
+		g-use-dma;
+		phys = <&u2phy0_otg>;
+		phy-names = "usb2-phy";
+		status = "disabled";
+	};
+
+	usb_host0_ehci: usb@30080000 {
+		compatible = "generic-ehci";
+		reg = <0x30080000 0x20000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+		clock-names = "usbhost", "utmi";
+		phys = <&u2phy0_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@300a0000 {
+		compatible = "generic-ohci";
+		reg = <0x300a0000 0x20000>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
+		clock-names = "usbhost", "utmi";
+		phys = <&u2phy0_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host1_ehci: usb@300c0000 {
+		compatible = "generic-ehci";
+		reg = <0x300c0000 0x20000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+		clock-names = "usbhost", "utmi";
+		phys = <&u2phy1_otg>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host1_ohci: usb@300e0000 {
+		compatible = "generic-ohci";
+		reg = <0x300e0000 0x20000>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
+		clock-names = "usbhost", "utmi";
+		phys = <&u2phy1_otg>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host2_ehci: usb@30100000 {
+		compatible = "generic-ehci";
+		reg = <0x30100000 0x20000>;
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+		phys = <&u2phy1_host>;
+		phy-names = "usb";
+		clock-names = "usbhost", "utmi";
+		status = "disabled";
+	};
+
+	usb_host2_ohci: usb@30120000 {
+		compatible = "generic-ohci";
+		reg = <0x30120000 0x20000>;
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+		clock-names = "usbhost", "utmi";
+		phys = <&u2phy1_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
 	gmac: ethernet@30200000 {
 		compatible = "rockchip,rk3228-gmac";
 		reg = <0x30200000 0x10000>;
-- 
2.0.0

[toc] | [prev] | [next] | [standalone]

#1655731 — Re: [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x

FromHeiko Stuebner <heiko@sntech.de>
Date2017-06-01 22:30 +0200
SubjectRe: [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x
Message-ID<tNETf-7v6-1@gated-at.bofh.it>
In reply to#1653760
Hi William,

Am Mittwoch, 31. Mai 2017, 09:21:23 CEST schrieb William Wu:
> This patch adds usb otg/host controllers and phys nodes on rk322x.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
>  arch/arm/boot/dts/rk322x.dtsi | 138 +++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 137 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
> index df57413..d4bfd3c 100644
> --- a/arch/arm/boot/dts/rk322x.dtsi
> +++ b/arch/arm/boot/dts/rk322x.dtsi
> @@ -210,8 +210,61 @@
>  	};
>  
>  	grf: syscon@11000000 {
> -		compatible = "syscon";
> +		compatible = "syscon", "simple-mfd";
>  		reg = <0x11000000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		u2phy0: usb2-phy@760 {
> +			compatible = "rockchip,rk322x-usb2phy";

as commented on the driver-side some moments ago, compatibles should not
contain wildcards, so please make this
	"rockchip,rk3228-usb2phy"
instead.

Same below and also for the dwc2 node.


Thanks
Heiko

> +			reg = <0x0760 0x0c>;
> +			clocks = <&cru SCLK_OTGPHY0>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			clock-output-names = "usb480m_phy0";
> +			status = "disabled";
> +
> +			u2phy0_otg: otg-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "otg-bvalid", "otg-id",
> +						  "linestate";
> +				status = "disabled";
> +			};
> +
> +			u2phy0_host: host-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "linestate";
> +				status = "disabled";
> +			};
> +		};
> +
> +		u2phy1: usb2-phy@800 {
> +			compatible = "rockchip,rk322x-usb2phy";

rockchip,rk3228-usb2phy

> +			reg = <0x0800 0x0c>;
> +			clocks = <&cru SCLK_OTGPHY1>;
> +			clock-names = "phyclk";
> +			#clock-cells = <0>;
> +			clock-output-names = "usb480m_phy1";
> +			status = "disabled";
> +
> +			u2phy1_otg: otg-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "linestate";
> +				status = "disabled";
> +			};
> +
> +			u2phy1_host: host-port {
> +				#phy-cells = <0>;
> +				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "linestate";
> +				status = "disabled";
> +			};
> +		};
>  	};
>  
>  	uart0: serial@11010000 {
> @@ -467,6 +520,89 @@
>  		status = "disabled";
>  	};
>  
> +	usb_otg: usb@30040000 {
> +		compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",

rockchip,rk3228-usb

> +			     "snps,dwc2";
> +		reg = <0x30040000 0x40000>;
> +		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_OTG>;
> +		clock-names = "otg";
> +		dr_mode = "otg";
> +		g-np-tx-fifo-size = <16>;
> +		g-rx-fifo-size = <280>;
> +		g-tx-fifo-size = <256 128 128 64 32 16>;
> +		g-use-dma;
> +		phys = <&u2phy0_otg>;
> +		phy-names = "usb2-phy";
> +		status = "disabled";
> +	};
> +
> +	usb_host0_ehci: usb@30080000 {
> +		compatible = "generic-ehci";
> +		reg = <0x30080000 0x20000>;
> +		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
> +		clock-names = "usbhost", "utmi";
> +		phys = <&u2phy0_host>;
> +		phy-names = "usb";
> +		status = "disabled";
> +	};
> +
> +	usb_host0_ohci: usb@300a0000 {
> +		compatible = "generic-ohci";
> +		reg = <0x300a0000 0x20000>;
> +		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
> +		clock-names = "usbhost", "utmi";
> +		phys = <&u2phy0_host>;
> +		phy-names = "usb";
> +		status = "disabled";
> +	};
> +
> +	usb_host1_ehci: usb@300c0000 {
> +		compatible = "generic-ehci";
> +		reg = <0x300c0000 0x20000>;
> +		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
> +		clock-names = "usbhost", "utmi";
> +		phys = <&u2phy1_otg>;
> +		phy-names = "usb";
> +		status = "disabled";
> +	};
> +
> +	usb_host1_ohci: usb@300e0000 {
> +		compatible = "generic-ohci";
> +		reg = <0x300e0000 0x20000>;
> +		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
> +		clock-names = "usbhost", "utmi";
> +		phys = <&u2phy1_otg>;
> +		phy-names = "usb";
> +		status = "disabled";
> +	};
> +
> +	usb_host2_ehci: usb@30100000 {
> +		compatible = "generic-ehci";
> +		reg = <0x30100000 0x20000>;
> +		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
> +		phys = <&u2phy1_host>;
> +		phy-names = "usb";
> +		clock-names = "usbhost", "utmi";
> +		status = "disabled";
> +	};
> +
> +	usb_host2_ohci: usb@30120000 {
> +		compatible = "generic-ohci";
> +		reg = <0x30120000 0x20000>;
> +		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
> +		clock-names = "usbhost", "utmi";
> +		phys = <&u2phy1_host>;
> +		phy-names = "usb";
> +		status = "disabled";
> +	};
> +
>  	gmac: ethernet@30200000 {
>  		compatible = "rockchip,rk3228-gmac";
>  		reg = <0x30200000 0x10000>;
>

[toc] | [prev] | [next] | [standalone]

#1655832 — Re: [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x

Fromwlf <wulf@rock-chips.com>
Date2017-06-02 03:50 +0200
SubjectRe: [PATCH 1/2] ARM: dts: rockchip: add usb nodes on rk322x
Message-ID<tNJSV-2n1-1@gated-at.bofh.it>
In reply to#1655731
Dear Heiko,

在 2017年06月02日 04:22, Heiko Stuebner 写道:
> Hi William,
>
> Am Mittwoch, 31. Mai 2017, 09:21:23 CEST schrieb William Wu:
>> This patch adds usb otg/host controllers and phys nodes on rk322x.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>>   arch/arm/boot/dts/rk322x.dtsi | 138 +++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 137 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
>> index df57413..d4bfd3c 100644
>> --- a/arch/arm/boot/dts/rk322x.dtsi
>> +++ b/arch/arm/boot/dts/rk322x.dtsi
>> @@ -210,8 +210,61 @@
>>   	};
>>   
>>   	grf: syscon@11000000 {
>> -		compatible = "syscon";
>> +		compatible = "syscon", "simple-mfd";
>>   		reg = <0x11000000 0x1000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		u2phy0: usb2-phy@760 {
>> +			compatible = "rockchip,rk322x-usb2phy";
> as commented on the driver-side some moments ago, compatibles should not
> contain wildcards, so please make this
> 	"rockchip,rk3228-usb2phy"
> instead.
>
> Same below and also for the dwc2 node.
Thanks, I'll fix it immediately.
>
>
> Thanks
> Heiko
>
>> +			reg = <0x0760 0x0c>;
>> +			clocks = <&cru SCLK_OTGPHY0>;
>> +			clock-names = "phyclk";
>> +			#clock-cells = <0>;
>> +			clock-output-names = "usb480m_phy0";
>> +			status = "disabled";
>> +
>> +			u2phy0_otg: otg-port {
>> +				#phy-cells = <0>;
>> +				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> +				interrupt-names = "otg-bvalid", "otg-id",
>> +						  "linestate";
>> +				status = "disabled";
>> +			};
>> +
>> +			u2phy0_host: host-port {
>> +				#phy-cells = <0>;
>> +				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> +				interrupt-names = "linestate";
>> +				status = "disabled";
>> +			};
>> +		};
>> +
>> +		u2phy1: usb2-phy@800 {
>> +			compatible = "rockchip,rk322x-usb2phy";
> rockchip,rk3228-usb2phy
OK, I'll fix it immediately.
>
>> +			reg = <0x0800 0x0c>;
>> +			clocks = <&cru SCLK_OTGPHY1>;
>> +			clock-names = "phyclk";
>> +			#clock-cells = <0>;
>> +			clock-output-names = "usb480m_phy1";
>> +			status = "disabled";
>> +
>> +			u2phy1_otg: otg-port {
>> +				#phy-cells = <0>;
>> +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
>> +				interrupt-names = "linestate";
>> +				status = "disabled";
>> +			};
>> +
>> +			u2phy1_host: host-port {
>> +				#phy-cells = <0>;
>> +				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
>> +				interrupt-names = "linestate";
>> +				status = "disabled";
>> +			};
>> +		};
>>   	};
>>   
>>   	uart0: serial@11010000 {
>> @@ -467,6 +520,89 @@
>>   		status = "disabled";
>>   	};
>>   
>> +	usb_otg: usb@30040000 {
>> +		compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
> rockchip,rk3228-usb
OK, I'll fix it immediately.:-)
>
>> +			     "snps,dwc2";
>> +		reg = <0x30040000 0x40000>;
>> +		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_OTG>;
>> +		clock-names = "otg";
>> +		dr_mode = "otg";
>> +		g-np-tx-fifo-size = <16>;
>> +		g-rx-fifo-size = <280>;
>> +		g-tx-fifo-size = <256 128 128 64 32 16>;
>> +		g-use-dma;
>> +		phys = <&u2phy0_otg>;
>> +		phy-names = "usb2-phy";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host0_ehci: usb@30080000 {
>> +		compatible = "generic-ehci";
>> +		reg = <0x30080000 0x20000>;
>> +		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
>> +		clock-names = "usbhost", "utmi";
>> +		phys = <&u2phy0_host>;
>> +		phy-names = "usb";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host0_ohci: usb@300a0000 {
>> +		compatible = "generic-ohci";
>> +		reg = <0x300a0000 0x20000>;
>> +		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_HOST0>, <&u2phy0>;
>> +		clock-names = "usbhost", "utmi";
>> +		phys = <&u2phy0_host>;
>> +		phy-names = "usb";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host1_ehci: usb@300c0000 {
>> +		compatible = "generic-ehci";
>> +		reg = <0x300c0000 0x20000>;
>> +		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
>> +		clock-names = "usbhost", "utmi";
>> +		phys = <&u2phy1_otg>;
>> +		phy-names = "usb";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host1_ohci: usb@300e0000 {
>> +		compatible = "generic-ohci";
>> +		reg = <0x300e0000 0x20000>;
>> +		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_HOST1>, <&u2phy1>;
>> +		clock-names = "usbhost", "utmi";
>> +		phys = <&u2phy1_otg>;
>> +		phy-names = "usb";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host2_ehci: usb@30100000 {
>> +		compatible = "generic-ehci";
>> +		reg = <0x30100000 0x20000>;
>> +		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
>> +		phys = <&u2phy1_host>;
>> +		phy-names = "usb";
>> +		clock-names = "usbhost", "utmi";
>> +		status = "disabled";
>> +	};
>> +
>> +	usb_host2_ohci: usb@30120000 {
>> +		compatible = "generic-ohci";
>> +		reg = <0x30120000 0x20000>;
>> +		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
>> +		clock-names = "usbhost", "utmi";
>> +		phys = <&u2phy1_host>;
>> +		phy-names = "usb";
>> +		status = "disabled";
>> +	};
>> +
>>   	gmac: ethernet@30200000 {
>>   		compatible = "rockchip,rk3228-gmac";
>>   		reg = <0x30200000 0x10000>;
>>
>
>
>
>

[toc] | [prev] | [next] | [standalone]

#1653761 — [PATCH 2/2] ARM: dts: rockchip: enable usb for rk3229 evb board

FromWilliam Wu <william.wu@rock-chips.com>
Date2017-05-31 03:30 +0200
Subject[PATCH 2/2] ARM: dts: rockchip: enable usb for rk3229 evb board
Message-ID<tN0Ct-6qZ-11@gated-at.bofh.it>
In reply to#1653759
Rockchip's rk3229 evaluation board has one usb otg controller
and three usb host controllers. Each usb controller connect
with one usb2 phy port through UTMI+ interface. And the three
usb host interfaces use the same GPIO VBUS drive. Let's enable
them to support usb on rk3229 evb board.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
 arch/arm/boot/dts/rk3229-evb.dts | 74 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 275092a..1b55192 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -58,6 +58,17 @@
 		#clock-cells = <0>;
 	};
 
+	vcc_host: vcc-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&host_vbus_drv>;
+		regulator-name = "vcc_host";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -85,6 +96,69 @@
 	status = "okay";
 };
 
+&pinctrl {
+	usb {
+		host_vbus_drv: host-vbus-drv {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
 &uart2 {
 	status = "okay";
 };
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc_host>;
+		status = "okay";
+	};
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host2_ehci {
+	status = "okay";
+};
+
+&usb_host2_ohci {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
-- 
2.0.0

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web