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[PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs

Started byIcenowy Zheng <icenowy@aosc.io>
First post2017-05-27 12:30 +0200
Last post2017-05-29 18:40 +0200
Articles 3 — 3 participants

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  [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs Icenowy Zheng <icenowy@aosc.io> - 2017-05-27 12:30 +0200
    Re: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10,  A20 and R40 SoCs Chen-Yu Tsai <wens@csie.org> - 2017-05-28 17:00 +0200
    Re: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10,  A20 and R40 SoCs Linus Walleij <linus.walleij@linaro.org> - 2017-05-29 18:40 +0200

#1651839 — [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-05-27 12:30 +0200
Subject[PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
Message-ID<tLH8R-1Wq-15@gated-at.bofh.it>
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.

Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v3:
- Commit message change.

 drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index a9d315a1256c..1bfc0d8a55df 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -87,6 +87,9 @@
 #define PINCTRL_SUN5I_GR8	BIT(3)
 #define PINCTRL_SUN6I_A31	BIT(4)
 #define PINCTRL_SUN6I_A31S	BIT(5)
+#define PINCTRL_SUN4I_A10	BIT(6)
+#define PINCTRL_SUN7I_A20	BIT(7)
+#define PINCTRL_SUN8I_R40	BIT(8)
 
 struct sunxi_desc_function {
 	unsigned long	variant;
-- 
2.12.2

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#1652155 — Re: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-28 17:00 +0200
SubjectRe: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
Message-ID<tM7PI-3iO-15@gated-at.bofh.it>
In reply to#1651839
On Sat, May 27, 2017 at 6:23 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>
> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
> into A10 driver, and add R40 support into it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

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#1652641 — Re: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs

FromLinus Walleij <linus.walleij@linaro.org>
Date2017-05-29 18:40 +0200
SubjectRe: [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
Message-ID<tMvS2-2uZ-3@gated-at.bofh.it>
In reply to#1651839
On Sat, May 27, 2017 at 12:23 PM, Icenowy Zheng <icenowy@aosc.io> wrote:

> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>
> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
> into A10 driver, and add R40 support into it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v3:
> - Commit message change.

Patch applied with Chen-Yu's review tag.

Yours,
Linus Walleij

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