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| Started by | Fabio Estevam <festevam@gmail.com> |
|---|---|
| First post | 2017-05-29 13:20 +0200 |
| Last post | 2017-05-29 13:20 +0200 |
| Articles | 1 — 1 participant |
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Re: [PATCH 3/4] mmc: sdhci-esdhc-imx: Allow all supported prescaler values Fabio Estevam <festevam@gmail.com> - 2017-05-29 13:20 +0200
| From | Fabio Estevam <festevam@gmail.com> |
|---|---|
| Date | 2017-05-29 13:20 +0200 |
| Subject | Re: [PATCH 3/4] mmc: sdhci-esdhc-imx: Allow all supported prescaler values |
| Message-ID | <tMqSl-7ws-1@gated-at.bofh.it> |
On Wed, May 3, 2017 at 7:05 AM, Benoît Thébaudeau <benoit@wsystem.com> wrote: > On i.MX, SYSCTL.SDCLKFS may always be set to 0 in order to make the SD > clock frequency prescaler divide by 1 in SDR mode, even with the eSDHC. > The previous minimum prescaler value of 2 in SDR mode with the eSDHC was > a code remnant from PowerPC, which actually has this limitation on > earlier revisions. > > In DDR mode, the prescaler can divide by up to 512. > > The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25, > this change makes it possible to get 48 MHz from the USB PLL > (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL > (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2). > > Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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