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| Started by | Benoît Thébaudeau <benoit@wsystem.com> |
|---|---|
| First post | 2017-05-30 11:20 +0200 |
| Last post | 2017-05-30 11:20 +0200 |
| Articles | 1 — 1 participant |
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[PATCH v3 2/5] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR Benoît Thébaudeau <benoit@wsystem.com> - 2017-05-30 11:20 +0200
| From | Benoît Thébaudeau <benoit@wsystem.com> |
|---|---|
| Date | 2017-05-30 11:20 +0200 |
| Subject | [PATCH v3 2/5] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR |
| Message-ID | <tMLtN-5qE-57@gated-at.bofh.it> |
The eSDHC can only DMA from 32-bit-aligned addresses. This fixes the following test cases of mmc_test: 11: Badly aligned write 12: Badly aligned read 13: Badly aligned multi-block write 14: Badly aligned multi-block read Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> --- Changes v1 -> v2: none. Changes v2 -> v3: none. --- drivers/mmc/host/sdhci-esdhc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h index c4bbd74..e7893f2 100644 --- a/drivers/mmc/host/sdhci-esdhc.h +++ b/drivers/mmc/host/sdhci-esdhc.h @@ -19,6 +19,7 @@ */ #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ + SDHCI_QUIRK_32BIT_DMA_ADDR | \ SDHCI_QUIRK_NO_BUSY_IRQ | \ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ SDHCI_QUIRK_PIO_NEEDS_DELAY | \ -- 2.7.4
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