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RE: [PATCH] pinctrl/amd: Use regular interrupt instead of chained

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  RE: [PATCH] pinctrl/amd: Use regular interrupt instead of chained "Shah, Nehal-bakulchandra" <Nehal-bakulchandra.Shah@amd.com> - 2017-05-26 07:00 +0200
    RE: [PATCH] pinctrl/amd: Use regular interrupt instead of chained Thomas Gleixner <tglx@linutronix.de> - 2017-05-26 08:50 +0200
      RE: [PATCH] pinctrl/amd: Use regular interrupt instead of chained "Shah, Nehal-bakulchandra" <Nehal-bakulchandra.Shah@amd.com> - 2017-05-26 11:40 +0200
        Re: [PATCH] pinctrl/amd: Use regular interrupt instead of chained Borislav Petkov <bp@alien8.de> - 2017-05-26 12:00 +0200

#1651078 — RE: [PATCH] pinctrl/amd: Use regular interrupt instead of chained

Hi Thomas,

Thanks for the patch. However, we have received this issue from multiple people and different disro but it occurs only on Gigabyte hardware. With reference AM4 ryzen board we are not facing this issue.
We are in discussion with gigabyte to check the BIOS part. Once we have clarity on that, we can consider driver part. Also, this code is running on multiple platform of different customers so changing directly at this point of time may be risky in my point of view. Requesting you to hold this patch till we get clarity on bios end.

Thanks for your understanding.

Regards

Nehal

-----Original Message-----
From: linux-gpio-owner@vger.kernel.org [mailto:linux-gpio-owner@vger.kernel.org] On Behalf Of Thomas Gleixner
Sent: Wednesday, May 24, 2017 2:54 AM
To: LKML <linux-kernel@vger.kernel.org>
Cc: Linus Walleij <linus.walleij@linaro.org>; linux-gpio@vger.kernel.org; Borislav Petkov <bp@alien8.de>; Xue, Ken <Ken.Xue@amd.com>
Subject: [PATCH] pinctrl/amd: Use regular interrupt instead of chained

The AMD pinctrl driver uses a chained interrupt to demultiplex the GPIO interrupts. Kevin Vandeventer reported, that his new AMD Ryzen locks up hard on boot when the AMD pinctrl driver is initialized. The reason is an interrupt storm. It's not clear whether that's caused by hardware or firmware or both.

Using chained interrupts on X86 is a dangerous endavour. If a system is misconfigured or the hardware buggy there is no safety net to catch an interrupt storm.

Convert the driver to use a regular interrupt for the demultiplex handler. This allows the interrupt storm detector to catch the malfunction and lets the system boot up.

This should be backported to stable because it's likely that more users run into this problem as the AMD Ryzen machines are spreading.

Reported-by: Kevin Vandeventer
Link: https://bugzilla.suse.com/show_bug.cgi?id=1034261
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 drivers/pinctrl/pinctrl-amd.c |   91 ++++++++++++++++++------------------------
 1 file changed, 41 insertions(+), 50 deletions(-)

--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -495,64 +495,54 @@ static struct irq_chip amd_gpio_irqchip
 	.flags        = IRQCHIP_SKIP_SET_WAKE,
 };
 
-static void amd_gpio_irq_handler(struct irq_desc *desc)
+#define PIN_IRQ_PENDING	(BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
+
+static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
 {
-	u32 i;
-	u32 off;
-	u32 reg;
-	u32 pin_reg;
-	u64 reg64;
-	int handled = 0;
-	unsigned int irq;
+	struct amd_gpio *gpio_dev = dev_id;
+	struct gpio_chip *gc = &gpio_dev->gc;
+	irqreturn_t ret = IRQ_NONE;
+	unsigned int i, irqnr;
 	unsigned long flags;
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+	u32 *regs, regval;
+	u64 status, mask;
 
-	chained_irq_enter(chip, desc);
-	/*enable GPIO interrupt again*/
+	/* Read the wake status */
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
-	reg64 = reg;
-	reg64 = reg64 << 32;
-
-	reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
-	reg64 |= reg;
+	status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
+	status <<= 32;
+	status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
-	/*
-	 * first 46 bits indicates interrupt status.
-	 * one bit represents four interrupt sources.
-	*/
-	for (off = 0; off < 46 ; off++) {
-		if (reg64 & BIT(off)) {
-			for (i = 0; i < 4; i++) {
-				pin_reg = readl(gpio_dev->base +
-						(off * 4 + i) * 4);
-				if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
-					(pin_reg & BIT(WAKE_STS_OFF))) {
-					irq = irq_find_mapping(gc->irqdomain,
-								off * 4 + i);
-					generic_handle_irq(irq);
-					writel(pin_reg,
-						gpio_dev->base
-						+ (off * 4 + i) * 4);
-					handled++;
-				}
-			}
+	/* Bit 0-45 contain the relevant status bits */
+	status &= (1ULL << 46) - 1;
+	regs = gpio_dev->base;
+	for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
+		if (!(status & mask))
+			continue;
+		status &= ~mask;
+
+		/* Each status bit covers four pins */
+		for (i = 0; i < 4; i++) {
+			regval = readl(regs + i);
+			if (!(regval & PIN_IRQ_PENDING))
+				continue;
+			irq = irq_find_mapping(gc->irqdomain, irqnr + i);
+			generic_handle_irq(irq);
+			/* Clear interrupt */
+			writel(regval, regs + i);
+			ret = IRQ_HANDLED;
 		}
 	}
 
-	if (handled == 0)
-		handle_bad_irq(desc);
-
+	/* Signal EOI to the GPIO unit */
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
-	reg |= EOI_MASK;
-	writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
+	regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
+	regval |= EOI_MASK;
+	writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
-	chained_irq_exit(chip, desc);
+	return ret;
 }
 
 static int amd_get_groups_count(struct pinctrl_dev *pctldev) @@ -821,10 +811,11 @@ static int amd_gpio_probe(struct platfor
 		goto out2;
 	}
 
-	gpiochip_set_chained_irqchip(&gpio_dev->gc,
-				 &amd_gpio_irqchip,
-				 irq_base,
-				 amd_gpio_irq_handler);
+	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
+			       KBUILD_MODNAME, gpio_dev);
+	if (ret)
+		goto out2;
+
 	platform_set_drvdata(pdev, gpio_dev);
 
 	dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
--
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#1651107

Nehal,

On Fri, 26 May 2017, Shah, Nehal-bakulchandra wrote:
> Thanks for the patch. However, we have received this issue from multiple
> people and different disro but it occurs only on Gigabyte hardware. With
> reference AM4 ryzen board we are not facing this issue.  We are in
> discussion with gigabyte to check the BIOS part. Once we have clarity on
> that, we can consider driver part. Also, this code is running on multiple
> platform of different customers so changing directly at this point of
> time may be risky in my point of view. Requesting you to hold this patch
> till we get clarity on bios end.

It does not matter at all whether this is a problem only on GB
hardware. Fact is, that this happened and it will happen again.

The patch does not change any functionality of the driver, it merily makes
it more robust and spares users the bloody annoying experience of a non
booting machine and the tedious task of figuring out why.

The main objective of the kernel is robustness and not pleasing the ego of
silicon vendors. We can't prevent the stupidity of BIOS people, we merily
can deal with it.

That patch should go into mainline ASAP and backported to stable in order
to help those people who bought wreckaged hardware.

Thanks,

	tglx

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#1651268

Hi Thomas,

Thanks  for the prompt reply. Agree on points.

we will validate at our end and shall provide the update.


Nehal
-----Original Message-----
From: Thomas Gleixner [mailto:tglx@linutronix.de] 
Sent: Friday, May 26, 2017 12:19 PM
To: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@amd.com>
Cc: LKML <linux-kernel@vger.kernel.org>; Linus Walleij <linus.walleij@linaro.org>; linux-gpio@vger.kernel.org; Borislav Petkov <bp@alien8.de>; Xue, Ken <Ken.Xue@amd.com>; S-k, Shyam-sundar <Shyam-sundar.S-k@amd.com>; stable@vger.kernel.org
Subject: RE: [PATCH] pinctrl/amd: Use regular interrupt instead of chained

Nehal,

On Fri, 26 May 2017, Shah, Nehal-bakulchandra wrote:
> Thanks for the patch. However, we have received this issue from 
> multiple people and different disro but it occurs only on Gigabyte 
> hardware. With reference AM4 ryzen board we are not facing this issue.  
> We are in discussion with gigabyte to check the BIOS part. Once we 
> have clarity on that, we can consider driver part. Also, this code is 
> running on multiple platform of different customers so changing 
> directly at this point of time may be risky in my point of view. 
> Requesting you to hold this patch till we get clarity on bios end.

It does not matter at all whether this is a problem only on GB hardware. Fact is, that this happened and it will happen again.

The patch does not change any functionality of the driver, it merily makes it more robust and spares users the bloody annoying experience of a non booting machine and the tedious task of figuring out why.

The main objective of the kernel is robustness and not pleasing the ego of silicon vendors. We can't prevent the stupidity of BIOS people, we merily can deal with it.

That patch should go into mainline ASAP and backported to stable in order to help those people who bought wreckaged hardware.

Thanks,

	tglx

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#1651278

On Fri, May 26, 2017 at 09:33:10AM +0000, Shah, Nehal-bakulchandra wrote:
> Hi Thomas,
> 
> Thanks  for the prompt reply. Agree on points.
> 
> we will validate at our end and shall provide the update.

First of all, please do not top-post.

What update are you talking about? The patch needs to go in regardless.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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