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Groups > linux.kernel > #1643130 > unrolled thread

[PATCH 00/12] arm64: dts: hi3660: add device nodes

Started byGuodong Xu <guodong.xu@linaro.org>
First post2017-05-17 10:40 +0200
Last post2017-05-23 13:30 +0200
Articles 17 — 2 participants

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Contents

  [PATCH 00/12] arm64: dts: hi3660: add device nodes Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:40 +0200
    [PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:40 +0200
      Re: [PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for  HiKey960 board Rob Herring <robh@kernel.org> - 2017-05-23 02:40 +0200
    [PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960 Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:40 +0200
      Re: [PATCH 02/12] arm64: dts: hisilicon: update compatible string  for hikey960 Rob Herring <robh@kernel.org> - 2017-05-23 02:40 +0200
    [PATCH 11/12] arm64: dts: hi3660: add power key dts node Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:40 +0200
      Re: [PATCH 11/12] arm64: dts: hi3660: add power key dts node Rob Herring <robh@kernel.org> - 2017-05-23 02:50 +0200
    [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:40 +0200
      Re: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes Rob Herring <robh@kernel.org> - 2017-05-23 02:50 +0200
        Re: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes Guodong Xu <guodong.xu@linaro.org> - 2017-05-23 11:30 +0200
    [PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:50 +0200
      Re: [PATCH 04/12] arm64: dts: hi3660: add resources for clock and  reset Rob Herring <robh@kernel.org> - 2017-05-23 02:50 +0200
    [PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:50 +0200
      Re: [PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node Rob Herring <robh@kernel.org> - 2017-05-23 02:50 +0200
    [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC Guodong Xu <guodong.xu@linaro.org> - 2017-05-17 10:50 +0200
      Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for  Hisilicon Hi3660 SOC Rob Herring <robh@kernel.org> - 2017-05-23 02:50 +0200
        Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for  Hisilicon Hi3660 SOC Guodong Xu <guodong.xu@linaro.org> - 2017-05-23 13:30 +0200

#1643130 — [PATCH 00/12] arm64: dts: hi3660: add device nodes

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:40 +0200
Subject[PATCH 00/12] arm64: dts: hi3660: add device nodes
Message-ID<tI2EV-J3-5@gated-at.bofh.it>
This patchset adds various devices nodes for hi3660 and hikey960.

HiKey960 is one of 96boards. For details information about it, please
refer to [1].

[1] https://github.com/96boards/documentation/tree/master/ConsumerEdition/HiKey960

Chen Feng (2):
  arm64: dts: hi3660: Add uarts nodes
  arm64: dts: hi3660: Add pl031 rtc node

Chen Jun (1):
  arm64: dts: hi3660: add power key dts node

Guodong Xu (4):
  dt-bindings: arm: hisilicon: add bindings for HiKey960 board
  arm64: dts: hisilicon: update compatible string for hikey960
  arm64: dts: hikey960: add WL1837 Bluetooth device node
  arm64: dts: hikey960: add LED nodes

Wang Xiaoyin (3):
  arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig
  arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
  arm64: dts: hi3660: add spi device nodes

Zhangfei Gao (2):
  arm64: dts: hi3660: add resources for clock and reset
  arm64: dts: Add I2C nodes for Hi3660

 .../bindings/arm/hisilicon/hisilicon.txt           |   4 +
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts  | 122 +++-
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi          | 616 +++++++++++++++-
 .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 779 +++++++++++++++++++--
 4 files changed, 1448 insertions(+), 73 deletions(-)

-- 
2.10.2

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#1643132 — [PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:40 +0200
Subject[PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board
Message-ID<tI2EX-J3-37@gated-at.bofh.it>
In reply to#1643130
Add bindings for HiKey960 Board.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 2e73215..7111fbc8 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -4,6 +4,10 @@ Hi3660 SoC
 Required root node properties:
 	- compatible = "hisilicon,hi3660";
 
+HiKey960 Board
+Required root node properties:
+	- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+
 Hi3798cv200 SoC
 Required root node properties:
 	- compatible = "hisilicon,hi3798cv200";
-- 
2.10.2

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#1647511 — Re: [PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:40 +0200
SubjectRe: [PATCH 01/12] dt-bindings: arm: hisilicon: add bindings for HiKey960 board
Message-ID<tK61H-4fZ-1@gated-at.bofh.it>
In reply to#1643132
On Wed, May 17, 2017 at 04:37:34PM +0800, Guodong Xu wrote:
> Add bindings for HiKey960 Board.
> 
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> ---
>  Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
>  1 file changed, 4 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

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#1643135 — [PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:40 +0200
Subject[PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960
Message-ID<tI2EX-J3-45@gated-at.bofh.it>
In reply to#1643130
Update compatible string for hikey960. HiKey960 is a develpment board built
with SoC Hi3660.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 186251f..64875a5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -12,7 +12,7 @@
 
 / {
 	model = "HiKey960";
-	compatible = "hisilicon,hi3660";
+	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
 
 	aliases {
 		serial5 = &uart5;       /* console UART */
-- 
2.10.2

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#1647515 — Re: [PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:40 +0200
SubjectRe: [PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960
Message-ID<tK61I-4fZ-13@gated-at.bofh.it>
In reply to#1643135
On Wed, May 17, 2017 at 04:37:35PM +0800, Guodong Xu wrote:
> Update compatible string for hikey960. HiKey960 is a develpment board built
> with SoC Hi3660.
> 
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

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#1643137 — [PATCH 11/12] arm64: dts: hi3660: add power key dts node

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:40 +0200
Subject[PATCH 11/12] arm64: dts: hi3660: add power key dts node
Message-ID<tI2EX-J3-51@gated-at.bofh.it>
In reply to#1643130
From: Chen Jun <chenjun14@huawei.com>

We use gpio_034 as power key on hikey960, and set gpio with pull-up
state, when key press the voltage on the gpio will come to lower, and
power key event will be reported.

Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 79735ee..6de86c0 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -10,6 +10,8 @@
 #include "hi3660.dtsi"
 #include "hikey960-pinctrl.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "HiKey960";
@@ -32,6 +34,21 @@
 		/* rewrite this at bootloader */
 		reg = <0x0 0x0 0x0 0x0>;
 	};
+
+	soc {
+		keys: gpio-keys {
+			compatible = "gpio-keys";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
+
+			power {
+				wakeup-source;
+				gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+				label = "GPIO Power";
+				linux,code = <KEY_POWER>;
+			};
+		};
+	};
 };
 
 &i2c0 {
-- 
2.10.2

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#1647532 — Re: [PATCH 11/12] arm64: dts: hi3660: add power key dts node

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:50 +0200
SubjectRe: [PATCH 11/12] arm64: dts: hi3660: add power key dts node
Message-ID<tK6bo-4ju-31@gated-at.bofh.it>
In reply to#1643137
On Wed, May 17, 2017 at 04:37:44PM +0800, Guodong Xu wrote:
> From: Chen Jun <chenjun14@huawei.com>
> 
> We use gpio_034 as power key on hikey960, and set gpio with pull-up
> state, when key press the voltage on the gpio will come to lower, and
> power key event will be reported.
> 
> Signed-off-by: Chen Jun <chenjun14@huawei.com>
> Signed-off-by: John Stultz <john.stultz@linaro.org>
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index 79735ee..6de86c0 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -10,6 +10,8 @@
>  #include "hi3660.dtsi"
>  #include "hikey960-pinctrl.dtsi"
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
>  
>  / {
>  	model = "HiKey960";
> @@ -32,6 +34,21 @@
>  		/* rewrite this at bootloader */
>  		reg = <0x0 0x0 0x0 0x0>;
>  	};
> +
> +	soc {
> +		keys: gpio-keys {

This isn't part of the SoC, so it should move out of the soc node.

> +			compatible = "gpio-keys";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
> +
> +			power {
> +				wakeup-source;
> +				gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
> +				label = "GPIO Power";
> +				linux,code = <KEY_POWER>;
> +			};
> +		};
> +	};
>  };
>  
>  &i2c0 {
> -- 
> 2.10.2
>

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#1643138 — [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:40 +0200
Subject[PATCH 07/12] arm64: dts: hi3660: Add uarts nodes
Message-ID<tI2EX-J3-49@gated-at.bofh.it>
In reply to#1643130
From: Chen Feng <puck.chen@hisilicon.com>

Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
Enable uart3 and uart6, disable uart5, in hikey960 board dts.

On HiKey960:
 - UART6 is used as default console, and is wired out through low speed
         expansion connector.
 - UART3 has RTS/CTS hardware handshake, and is wired out through low
         speed expansion connector.
 - UART5 is not used in commercial launched boards. So disable it.
 - UART4 is connected to Bluetooth, WL1837.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++--
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 60 +++++++++++++++++++++++
 2 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index f685b1e..513c496 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -15,12 +15,16 @@
 	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
 
 	aliases {
-		serial5 = &uart5;       /* console UART */
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		serial6 = &uart6;
 	};
 
-	chosen {
-		stdout-path = "serial5:115200n8";
-	};
+	chosen {};
 
 	memory@0 {
 		device_type = "memory";
@@ -47,6 +51,10 @@
 	status = "okay";
 };
 
-&uart5 {
+&uart3 {
+	status = "okay";
+};
+
+&uart6 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3bea0d2..0951a29 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -242,6 +242,56 @@
 			status = "disabled";
 		};
 
+		uart0: serial@fdf02000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf02000 0x0 0x1000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: serial@fdf00000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf00000 0x0 0x1000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
+				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: serial@fdf03000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf03000 0x0 0x1000>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart3: serial@ffd74000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xffd74000 0x0 0x1000>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart4: serial@fdf01000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfdf01000 0x0 0x1000>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
+				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
 		uart5: serial@fdf05000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xfdf05000 0x0 0x1000>;
@@ -252,6 +302,16 @@
 			status = "disabled";
 		};
 
+		uart6: serial@fff32000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xfff32000 0x0 0x1000>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_UART6>,
+				 <&crg_ctrl HI3660_PCLK>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
 		gpio0: gpio@e8a0b000 {
 			compatible = "arm,pl061", "arm,primecell";
 			reg = <0 0xe8a0b000 0 0x1000>;
-- 
2.10.2

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#1647520 — Re: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:50 +0200
SubjectRe: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes
Message-ID<tK6bn-4ju-9@gated-at.bofh.it>
In reply to#1643138
On Wed, May 17, 2017 at 04:37:40PM +0800, Guodong Xu wrote:
> From: Chen Feng <puck.chen@hisilicon.com>
> 
> Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
> Enable uart3 and uart6, disable uart5, in hikey960 board dts.
> 
> On HiKey960:
>  - UART6 is used as default console, and is wired out through low speed
>          expansion connector.
>  - UART3 has RTS/CTS hardware handshake, and is wired out through low
>          speed expansion connector.
>  - UART5 is not used in commercial launched boards. So disable it.
>  - UART4 is connected to Bluetooth, WL1837.
> 
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
> Reviewed-by: Zhangfei Gao <zhangfei.gao@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++--
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 60 +++++++++++++++++++++++
>  2 files changed, 73 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> index f685b1e..513c496 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
> @@ -15,12 +15,16 @@
>  	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
>  
>  	aliases {
> -		serial5 = &uart5;       /* console UART */
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +		serial4 = &uart4;
> +		serial5 = &uart5;
> +		serial6 = &uart6;
>  	};
>  
> -	chosen {
> -		stdout-path = "serial5:115200n8";

Why is this removed?

> -	};
> +	chosen {};
>  
>  	memory@0 {
>  		device_type = "memory";
> @@ -47,6 +51,10 @@
>  	status = "okay";
>  };
>  
> -&uart5 {
> +&uart3 {
> +	status = "okay";
> +};
> +
> +&uart6 {
>  	status = "okay";

labels for LS connector?

>  };
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 3bea0d2..0951a29 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -242,6 +242,56 @@
>  			status = "disabled";
>  		};
>  
> +		uart0: serial@fdf02000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf02000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@fdf00000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf00000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
> +				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@fdf03000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf03000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@ffd74000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xffd74000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@fdf01000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfdf01000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
> +				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
>  		uart5: serial@fdf05000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0x0 0xfdf05000 0x0 0x1000>;
> @@ -252,6 +302,16 @@
>  			status = "disabled";
>  		};
>  
> +		uart6: serial@fff32000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x0 0xfff32000 0x0 0x1000>;
> +			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&crg_ctrl HI3660_CLK_UART6>,
> +				 <&crg_ctrl HI3660_PCLK>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
>  		gpio0: gpio@e8a0b000 {
>  			compatible = "arm,pl061", "arm,primecell";
>  			reg = <0 0xe8a0b000 0 0x1000>;
> -- 
> 2.10.2
>

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#1647880 — Re: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-23 11:30 +0200
SubjectRe: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes
Message-ID<tKeiC-1cT-27@gated-at.bofh.it>
In reply to#1647520
On Tue, May 23, 2017 at 8:44 AM, Rob Herring <robh@kernel.org> wrote:
> On Wed, May 17, 2017 at 04:37:40PM +0800, Guodong Xu wrote:
>> From: Chen Feng <puck.chen@hisilicon.com>
>>
>> Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
>> Enable uart3 and uart6, disable uart5, in hikey960 board dts.
>>
>> On HiKey960:
>>  - UART6 is used as default console, and is wired out through low speed
>>          expansion connector.
>>  - UART3 has RTS/CTS hardware handshake, and is wired out through low
>>          speed expansion connector.
>>  - UART5 is not used in commercial launched boards. So disable it.
>>  - UART4 is connected to Bluetooth, WL1837.
>>
>> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
>> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
>> Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
>> Reviewed-by: Zhangfei Gao <zhangfei.gao@hisilicon.com>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++--
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 60 +++++++++++++++++++++++
>>  2 files changed, 73 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> index f685b1e..513c496 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -15,12 +15,16 @@
>>       compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
>>
>>       aliases {
>> -             serial5 = &uart5;       /* console UART */
>> +             serial0 = &uart0;
>> +             serial1 = &uart1;
>> +             serial2 = &uart2;
>> +             serial3 = &uart3;
>> +             serial4 = &uart4;
>> +             serial5 = &uart5;
>> +             serial6 = &uart6;
>>       };
>>
>> -     chosen {
>> -             stdout-path = "serial5:115200n8";
>
> Why is this removed?
>

I will add this back, but will change serial5 to 6. Serial6 is now the
default console.

serial5 is obsoleted on commercial boards.


>> -     };
>> +     chosen {};
>>
>>       memory@0 {
>>               device_type = "memory";
>> @@ -47,6 +51,10 @@
>>       status = "okay";
>>  };
>>
>> -&uart5 {
>> +&uart3 {
>> +     status = "okay";
>> +};
>> +
>> +&uart6 {
>>       status = "okay";
>
> labels for LS connector?
>

Yes, I Will add.

-Guodong

>>  };
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> index 3bea0d2..0951a29 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -242,6 +242,56 @@
>>                       status = "disabled";
>>               };
>>
>> +             uart0: serial@fdf02000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf02000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart1: serial@fdf00000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf00000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
>> +                              <&crg_ctrl HI3660_CLK_GATE_UART1>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart2: serial@fdf03000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf03000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart3: serial@ffd74000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xffd74000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>> +             uart4: serial@fdf01000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfdf01000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
>> +                              <&crg_ctrl HI3660_CLK_GATE_UART4>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>>               uart5: serial@fdf05000 {
>>                       compatible = "arm,pl011", "arm,primecell";
>>                       reg = <0x0 0xfdf05000 0x0 0x1000>;
>> @@ -252,6 +302,16 @@
>>                       status = "disabled";
>>               };
>>
>> +             uart6: serial@fff32000 {
>> +                     compatible = "arm,pl011", "arm,primecell";
>> +                     reg = <0x0 0xfff32000 0x0 0x1000>;
>> +                     interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> +                     clocks = <&crg_ctrl HI3660_CLK_UART6>,
>> +                              <&crg_ctrl HI3660_PCLK>;
>> +                     clock-names = "uartclk", "apb_pclk";
>> +                     status = "disabled";
>> +             };
>> +
>>               gpio0: gpio@e8a0b000 {
>>                       compatible = "arm,pl061", "arm,primecell";
>>                       reg = <0 0xe8a0b000 0 0x1000>;
>> --
>> 2.10.2
>>

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#1643143 — [PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:50 +0200
Subject[PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset
Message-ID<tI2OB-O8-1@gated-at.bofh.it>
In reply to#1643130
From: Zhangfei Gao <zhangfei.gao@linaro.org>

Add some resource nodes for clock and reset

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++----
 1 file changed, 46 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086..f55710a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi3660-clock.h>
 
 / {
 	compatible = "hisilicon,hi3660";
@@ -141,18 +142,56 @@
 		#size-cells = <2>;
 		ranges;
 
-		fixed_uart5: fixed_19_2M {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <19200000>;
-			clock-output-names = "fixed:uart5";
+		crg_ctrl: crg_ctrl@fff35000 {
+			compatible = "hisilicon,hi3660-crgctrl", "syscon";
+			reg = <0x0 0xfff35000 0x0 0x1000>;
+			#clock-cells = <1>;
 		};
 
-		uart5: uart@fdf05000 {
+		crg_rst: crg_rst_controller {
+			compatible = "hisilicon,hi3660-reset";
+			#reset-cells = <2>;
+			hisi,rst-syscon = <&crg_ctrl>;
+		};
+
+
+		pctrl: pctrl@e8a09000 {
+			compatible = "hisilicon,hi3660-pctrl", "syscon";
+			reg = <0x0 0xe8a09000 0x0 0x2000>;
+			#clock-cells = <1>;
+		};
+
+		pmuctrl: crg_ctrl@fff34000 {
+			compatible = "hisilicon,hi3660-pmuctrl", "syscon";
+			reg = <0x0 0xfff34000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		sctrl: sctrl@fff0a000 {
+			compatible = "hisilicon,hi3660-sctrl", "syscon";
+			reg = <0x0 0xfff0a000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		iomcu: iomcu@ffd7e000 {
+			compatible = "hisilicon,hi3660-iomcu", "syscon";
+			reg = <0x0 0xffd7e000 0x0 0x1000>;
+			#clock-cells = <1>;
+
+		};
+
+		iomcu_rst: reset {
+			compatible = "hisilicon,hi3660-reset";
+			hisi,rst-syscon = <&iomcu>;
+			#reset-cells = <2>;
+		};
+
+		uart5: serial@fdf05000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xfdf05000 0x0 0x1000>;
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&fixed_uart5 &fixed_uart5>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
+				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
-- 
2.10.2

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#1647537 — Re: [PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:50 +0200
SubjectRe: [PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset
Message-ID<tK6bp-4ju-53@gated-at.bofh.it>
In reply to#1643143
On Wed, May 17, 2017 at 04:37:37PM +0800, Guodong Xu wrote:
> From: Zhangfei Gao <zhangfei.gao@linaro.org>
> 
> Add some resource nodes for clock and reset
> 
> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++----
>  1 file changed, 46 insertions(+), 7 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

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#1643146 — [PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:50 +0200
Subject[PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node
Message-ID<tI2OC-O8-7@gated-at.bofh.it>
In reply to#1643130
From: Chen Feng <puck.chen@hisilicon.com>

Add dts node to enable pl031 rtc.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 0951a29..c2bca5d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -312,6 +312,14 @@
 			status = "disabled";
 		};
 
+		rtc0: rtc@fff04000 {
+			compatible = "arm,pl031", "arm,primecell";
+			reg = <0x0 0Xfff04000 0x0 0x1000>;
+			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_PCLK>;
+			clock-names = "apb_pclk";
+		};
+
 		gpio0: gpio@e8a0b000 {
 			compatible = "arm,pl061", "arm,primecell";
 			reg = <0 0xe8a0b000 0 0x1000>;
-- 
2.10.2

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#1647535 — Re: [PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:50 +0200
SubjectRe: [PATCH 09/12] arm64: dts: hi3660: Add pl031 rtc node
Message-ID<tK6bo-4ju-39@gated-at.bofh.it>
In reply to#1643146
On Wed, May 17, 2017 at 04:37:42PM +0800, Guodong Xu wrote:
> From: Chen Feng <puck.chen@hisilicon.com>
> 
> Add dts node to enable pl031 rtc.
> 
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

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#1643147 — [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-17 10:50 +0200
Subject[PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
Message-ID<tI2OC-O8-9@gated-at.bofh.it>
In reply to#1643130
From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>

This patch adds pl061 device nodes for Hi3660 SoC.

Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409 ++++++++++++++++++++++++++++++
 1 file changed, 409 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index f217c9d..3bea0d2 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -251,5 +251,414 @@
 			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
+
+		gpio0: gpio@e8a0b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0b000 0 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 1 0 7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio1: gpio@e8a0c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0c000 0 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 1 7 7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio2: gpio@e8a0d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0d000 0 0x1000>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 14 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio3: gpio@e8a0e000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0e000 0 0x1000>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 22 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio4: gpio@e8a0f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a0f000 0 0x1000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 30 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio5: gpio@e8a10000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a10000 0 0x1000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 38 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio6: gpio@e8a11000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a11000 0 0x1000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 46 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio7: gpio@e8a12000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a12000 0 0x1000>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 54 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio8: gpio@e8a13000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a13000 0 0x1000>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 62 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio9: gpio@e8a14000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a14000 0 0x1000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 70 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio10: gpio@e8a15000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a15000 0 0x1000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 78 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio11: gpio@e8a16000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a16000 0 0x1000>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 86 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio12: gpio@e8a17000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a17000 0 0x1000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio13: gpio@e8a18000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a18000 0 0x1000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 102 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio14: gpio@e8a19000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a19000 0 0x1000>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 110 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio15: gpio@e8a1a000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1a000 0 0x1000>;
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx0 0 118 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio16: gpio@e8a1b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1b000 0 0x1000>;
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio17: gpio@e8a1c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1c000 0 0x1000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio18: gpio@ff3b4000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xff3b4000 0 0x1000>;
+			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx2 0 0 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio19: gpio@ff3b5000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xff3b5000 0 0x1000>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx2 0 8 4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio20: gpio@e8a1f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a1f000 0 0x1000>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pmx1 0 0 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio21: gpio@e8a20000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xe8a20000 0 0x1000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&pmx3 0 0 6>;
+			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio22: gpio@fff0b000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0b000 0 0x1000>;
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO176 */
+			gpio-ranges = <&pmx4 2 0 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio23: gpio@fff0c000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0c000 0 0x1000>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO184 */
+			gpio-ranges = <&pmx4 0 6 7>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		 gpio24: gpio@fff0d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0d000 0 0x1000>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO192 */
+			gpio-ranges = <&pmx4 0 13 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio25: gpio@fff0e000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0e000 0 0x1000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO200 */
+			gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio26: gpio@fff0f000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff0f000 0 0x1000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO208 */
+			gpio-ranges = <&pmx4 0 28 8>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio27: gpio@fff10000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff10000 0 0x1000>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			/* GPIO216 */
+			gpio-ranges = <&pmx4 0 36 6>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
+
+		gpio28: gpio@fff1d000 {
+			compatible = "arm,pl061", "arm,primecell";
+			reg = <0 0xfff1d000 0 0x1000>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
+			clock-names = "apb_pclk";
+			status = "ok";
+		};
 	};
 };
-- 
2.10.2

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#1647539 — Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

FromRob Herring <robh@kernel.org>
Date2017-05-23 02:50 +0200
SubjectRe: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
Message-ID<tK6bo-4ju-43@gated-at.bofh.it>
In reply to#1643147
On Wed, May 17, 2017 at 04:37:39PM +0800, Guodong Xu wrote:
> From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> 
> This patch adds pl061 device nodes for Hi3660 SoC.
> 
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409 ++++++++++++++++++++++++++++++
>  1 file changed, 409 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index f217c9d..3bea0d2 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -251,5 +251,414 @@
>  			clock-names = "uartclk", "apb_pclk";
>  			status = "disabled";
>  		};
> +
> +		gpio0: gpio@e8a0b000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0b000 0 0x1000>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 1 0 7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
> +			clock-names = "apb_pclk";
> +			status = "ok";

You don't need "ok" here if these are default enabled.

> +		};
> +
> +		gpio1: gpio@e8a0c000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0c000 0 0x1000>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 1 7 7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
> +			clock-names = "apb_pclk";
> +			status = "ok";

ditto...

> +		};
> +
> +		gpio2: gpio@e8a0d000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0d000 0 0x1000>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 14 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio3: gpio@e8a0e000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0e000 0 0x1000>;
> +			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 22 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio4: gpio@e8a0f000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a0f000 0 0x1000>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 30 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio5: gpio@e8a10000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a10000 0 0x1000>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 38 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio6: gpio@e8a11000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a11000 0 0x1000>;
> +			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 46 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio7: gpio@e8a12000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a12000 0 0x1000>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 54 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio8: gpio@e8a13000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a13000 0 0x1000>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 62 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio9: gpio@e8a14000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a14000 0 0x1000>;
> +			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 70 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio10: gpio@e8a15000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a15000 0 0x1000>;
> +			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 78 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio11: gpio@e8a16000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a16000 0 0x1000>;
> +			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 86 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio12: gpio@e8a17000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a17000 0 0x1000>;
> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio13: gpio@e8a18000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a18000 0 0x1000>;
> +			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 102 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio14: gpio@e8a19000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a19000 0 0x1000>;
> +			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 110 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio15: gpio@e8a1a000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1a000 0 0x1000>;
> +			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx0 0 118 6>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio16: gpio@e8a1b000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1b000 0 0x1000>;
> +			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio17: gpio@e8a1c000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1c000 0 0x1000>;
> +			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio18: gpio@ff3b4000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xff3b4000 0 0x1000>;
> +			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx2 0 0 8>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio19: gpio@ff3b5000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xff3b5000 0 0x1000>;
> +			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx2 0 8 4>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio20: gpio@e8a1f000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a1f000 0 0x1000>;
> +			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&pmx1 0 0 6>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio21: gpio@e8a20000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xe8a20000 0 0x1000>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&pmx3 0 0 6>;
> +			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio22: gpio@fff0b000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xfff0b000 0 0x1000>;
> +			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			/* GPIO176 */
> +			gpio-ranges = <&pmx4 2 0 6>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		gpio23: gpio@fff0c000 {
> +			compatible = "arm,pl061", "arm,primecell";
> +			reg = <0 0xfff0c000 0 0x1000>;
> +			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			/* GPIO184 */
> +			gpio-ranges = <&pmx4 0 6 7>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
> +			clock-names = "apb_pclk";
> +			status = "ok";
> +		};
> +
> +		 gpio24: gpio@fff0d000 {

extra space     ^

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#1647947 — Re: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC

FromGuodong Xu <guodong.xu@linaro.org>
Date2017-05-23 13:30 +0200
SubjectRe: [PATCH 06/12] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
Message-ID<tKgaJ-2wv-1@gated-at.bofh.it>
In reply to#1647539
On Tue, May 23, 2017 at 8:41 AM, Rob Herring <robh@kernel.org> wrote:
> On Wed, May 17, 2017 at 04:37:39PM +0800, Guodong Xu wrote:
>> From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
>>
>> This patch adds pl061 device nodes for Hi3660 SoC.
>>
>> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 409 ++++++++++++++++++++++++++++++
>>  1 file changed, 409 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> index f217c9d..3bea0d2 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -251,5 +251,414 @@
>>                       clock-names = "uartclk", "apb_pclk";
>>                       status = "disabled";
>>               };
>> +
>> +             gpio0: gpio@e8a0b000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0b000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 1 0 7>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>
> You don't need "ok" here if these are default enabled.
>
>> +             };
>> +
>> +             gpio1: gpio@e8a0c000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0c000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 1 7 7>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>
> ditto...
>
>> +             };
>> +
>> +             gpio2: gpio@e8a0d000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0d000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 14 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio3: gpio@e8a0e000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0e000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 22 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio4: gpio@e8a0f000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a0f000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 30 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio5: gpio@e8a10000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a10000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 38 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio6: gpio@e8a11000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a11000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 46 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio7: gpio@e8a12000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a12000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 54 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio8: gpio@e8a13000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a13000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 62 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio9: gpio@e8a14000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a14000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 70 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio10: gpio@e8a15000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a15000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 78 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio11: gpio@e8a16000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a16000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 86 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio12: gpio@e8a17000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a17000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio13: gpio@e8a18000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a18000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 102 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio14: gpio@e8a19000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a19000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 110 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio15: gpio@e8a1a000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1a000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx0 0 118 6>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio16: gpio@e8a1b000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1b000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio17: gpio@e8a1c000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1c000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio18: gpio@ff3b4000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xff3b4000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx2 0 0 8>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio19: gpio@ff3b5000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xff3b5000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx2 0 8 4>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio20: gpio@e8a1f000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a1f000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     gpio-ranges = <&pmx1 0 0 6>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio21: gpio@e8a20000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xe8a20000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     gpio-ranges = <&pmx3 0 0 6>;
>> +                     clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio22: gpio@fff0b000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xfff0b000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     /* GPIO176 */
>> +                     gpio-ranges = <&pmx4 2 0 6>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +             gpio23: gpio@fff0c000 {
>> +                     compatible = "arm,pl061", "arm,primecell";
>> +                     reg = <0 0xfff0c000 0 0x1000>;
>> +                     interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     /* GPIO184 */
>> +                     gpio-ranges = <&pmx4 0 6 7>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
>> +                     clock-names = "apb_pclk";
>> +                     status = "ok";
>> +             };
>> +
>> +              gpio24: gpio@fff0d000 {
>
> extra space     ^

Thanks, Rob. I will fix this and all above.

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