Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1649562 > unrolled thread
| Started by | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| First post | 2017-05-24 14:20 +0200 |
| Last post | 2017-05-29 09:10 +0200 |
| Articles | 2 — 2 participants |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
[PATCH 2/3] ARM: sun8i: v3s: add PWM pinmux nodes Icenowy Zheng <icenowy@aosc.io> - 2017-05-24 14:20 +0200
Re: [PATCH 2/3] ARM: sun8i: v3s: add PWM pinmux nodes Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-05-29 09:10 +0200
| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-05-24 14:20 +0200 |
| Subject | [PATCH 2/3] ARM: sun8i: v3s: add PWM pinmux nodes |
| Message-ID | <tKDqG-2fU-7@gated-at.bofh.it> |
Allwinner V3s have two PWM channels, the first channel can be only at
PB4 pin, and the second channel PB5.
Add their pinmux configurations.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index bb080c4bd22c..db3328a2c89a 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -239,6 +239,16 @@
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
};
+
+ pwm0_pins: pwm0 {
+ pins = "PB4";
+ function = "pwm0";
+ };
+
+ pwm1_pins: pwm1 {
+ pins = "PB5";
+ function = "pwm1";
+ };
};
timer@01c20c00 {
--
2.12.2
[toc] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-05-29 09:10 +0200 |
| Message-ID | <tMmYq-4TV-7@gated-at.bofh.it> |
| In reply to | #1649562 |
[Multipart message — attachments visible in raw view] — view raw
Hi,
On Wed, May 24, 2017 at 08:13:19PM +0800, Icenowy Zheng wrote:
> Allwinner V3s have two PWM channels, the first channel can be only at
> PB4 pin, and the second channel PB5.
>
> Add their pinmux configurations.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index bb080c4bd22c..db3328a2c89a 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -239,6 +239,16 @@
> pins = "PC0", "PC1", "PC2", "PC3";
> function = "spi0";
> };
> +
> + pwm0_pins: pwm0 {
> + pins = "PB4";
> + function = "pwm0";
> + };
> +
> + pwm1_pins: pwm1 {
> + pins = "PB5";
> + function = "pwm1";
> + };
Please order the nodes alphabetically.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web