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RISC-V Linux Port v1

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Contents

  RISC-V Linux Port v1 Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 02:50 +0200
    [PATCH 5/7] RISC-V: arch/riscv/lib Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 02:50 +0200
      Re: [PATCH 5/7] RISC-V: arch/riscv/lib Geert Uytterhoeven <geert@linux-m68k.org> - 2017-05-23 12:50 +0200
        Re: [PATCH 5/7] RISC-V: arch/riscv/lib Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-24 00:10 +0200
      Re: [PATCH 5/7] RISC-V: arch/riscv/lib Arnd Bergmann <arnd@arndb.de> - 2017-05-23 13:30 +0200
    [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 02:50 +0200
      Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Olof Johansson <olof@lixom.net> - 2017-05-23 03:30 +0200
        Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Randy Dunlap <rdunlap@infradead.org> - 2017-05-23 03:40 +0200
          Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 06:50 +0200
        Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 06:50 +0200
          Re: [patches] Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Olof Johansson <olof@lixom.net> - 2017-05-23 07:20 +0200
            Re: [patches] Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and  Kconfigs Benjamin Herrenschmidt <benh@kernel.crashing.org> - 2017-05-23 23:10 +0200
      Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Olof Johansson <olof@lixom.net> - 2017-05-23 07:30 +0200
        Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 17:30 +0200
      Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Geert Uytterhoeven <geert@linux-m68k.org> - 2017-05-23 13:00 +0200
      Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs Arnd Bergmann <arnd@arndb.de> - 2017-05-23 13:50 +0200
    [PATCH 3/7] RISC-V: Device Tree Documentation Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 02:50 +0200
      Re: [PATCH 3/7] RISC-V: Device Tree Documentation Arnd Bergmann <arnd@arndb.de> - 2017-05-23 14:10 +0200
    Re: RISC-V Linux Port v1 Olof Johansson <olof@lixom.net> - 2017-05-23 03:20 +0200
      Re: RISC-V Linux Port v1 Randy Dunlap <rdunlap@infradead.org> - 2017-05-23 03:30 +0200
        Re: RISC-V Linux Port v1 Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 05:40 +0200
      Re: RISC-V Linux Port v1 Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 05:40 +0200
        Re: RISC-V Linux Port v1 Tobias Klauser <tklauser@distanz.ch> - 2017-05-23 08:50 +0200
          Re: RISC-V Linux Port v1 Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 17:50 +0200
    Re: RISC-V Linux Port v1 Randy Dunlap <rdunlap@infradead.org> - 2017-05-23 04:20 +0200
      Re: RISC-V Linux Port v1 Palmer Dabbelt <palmer@dabbelt.com> - 2017-05-23 06:50 +0200
    Re: [PATCH 6/7] RISC-V: arch/riscv/kernel Olof Johansson <olof@lixom.net> - 2017-05-23 04:20 +0200
    Re: [PATCH 4/7] RISC-V: arch/riscv/include Arnd Bergmann <arnd@arndb.de> - 2017-05-23 15:00 +0200
      Re: [PATCH 4/7] RISC-V: arch/riscv/include Benjamin Herrenschmidt <benh@kernel.crashing.org> - 2017-05-23 23:30 +0200
    Re: [PATCH 6/7] RISC-V: arch/riscv/kernel Arnd Bergmann <arnd@arndb.de> - 2017-05-23 15:40 +0200

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#1647525 — RISC-V Linux Port v1

We'd like to submit for inclusion in Linux a port for the RISC-V architecture.
While it is doubtlessly not complete, we think it is far enough along to start
the upstreaming process.  Our binutils and GCC ports have been accepted and
released, and we plan on submitting glibc patches soon.

This port targets Version 1.10 of the RISC-V Privileged ISA, and supports both
the RV32 and RV64 user ISAs.  The RISC-V community and the 60-some member
companies of the RISC-V Foundation are quite eager to have a single, standard
Linux port.  We thank you in advance for your help in this process and for your
feedback on the software contribution itself.

These patches build and boot on top of 4.12-rc2.  I understand that the merge
window is closed, but it was suggested that the best time to submit a new
architecture port would be right after an RC2 as the earliest point at which
the tree is usually generally churn-free enough.  While we optimistically hope
that we can get the port in for the 4.13 merge window, we're also eager to
ensure that the user-visible ABI is sane so we can proceed with our glibc port.
We'd like to at least get any user ABI issues shaken out as soon as possible,
even if we don't make it into 4.13.

Albert and I will volunteer to maintain this port if it's OK with everyone.

We'd like to thank the various members of the RISC-V software community who
have helped us with the port.

Thanks!

In addition to the threaded messages, our port can be found on Git Hib

  https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v1

[PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64}
[PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs
[PATCH 3/7] RISC-V: Device Tree Documentation
[PATCH 4/7] RISC-V: arch/riscv/include
[PATCH 5/7] RISC-V: arch/riscv/lib
[PATCH 6/7] RISC-V: arch/riscv/kernel
[PATCH 7/7] RISC-V: arch/riscv/mm

[toc] | [next] | [standalone]

#1647528 — [PATCH 5/7] RISC-V: arch/riscv/lib

---
 arch/riscv/lib/Makefile  |   5 ++
 arch/riscv/lib/ashldi3.c |  42 ++++++++++++++++
 arch/riscv/lib/ashrdi3.c |  44 +++++++++++++++++
 arch/riscv/lib/delay.c   |  42 ++++++++++++++++
 arch/riscv/lib/libgcc.h  |  46 +++++++++++++++++
 arch/riscv/lib/lshrdi3.c |  42 ++++++++++++++++
 arch/riscv/lib/memcpy.S  |  99 +++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/memset.S  | 119 ++++++++++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/uaccess.S | 125 +++++++++++++++++++++++++++++++++++++++++++++++
 9 files changed, 564 insertions(+)
 create mode 100644 arch/riscv/lib/Makefile
 create mode 100644 arch/riscv/lib/ashldi3.c
 create mode 100644 arch/riscv/lib/ashrdi3.c
 create mode 100644 arch/riscv/lib/delay.c
 create mode 100644 arch/riscv/lib/libgcc.h
 create mode 100644 arch/riscv/lib/lshrdi3.c
 create mode 100644 arch/riscv/lib/memcpy.S
 create mode 100644 arch/riscv/lib/memset.S
 create mode 100644 arch/riscv/lib/uaccess.S

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
new file mode 100644
index 000000000000..f644e582f4b8
--- /dev/null
+++ b/arch/riscv/lib/Makefile
@@ -0,0 +1,5 @@
+lib-y	:= delay.o memcpy.o memset.o uaccess.o
+
+ifeq ($(CONFIG_64BIT),)
+lib-y += ashldi3.o ashrdi3.o lshrdi3.o
+endif
diff --git a/arch/riscv/lib/ashldi3.c b/arch/riscv/lib/ashldi3.c
new file mode 100644
index 000000000000..9fb71e82ff16
--- /dev/null
+++ b/arch/riscv/lib/ashldi3.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 Darius Rad <darius@bluespec.com>
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/export.h>
+
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}
+EXPORT_SYMBOL(__ashldi3);
diff --git a/arch/riscv/lib/ashrdi3.c b/arch/riscv/lib/ashrdi3.c
new file mode 100644
index 000000000000..8a92e7e8de33
--- /dev/null
+++ b/arch/riscv/lib/ashrdi3.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2014 Darius Rad <darius@bluespec.com>
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/export.h>
+
+#include "libgcc.h"
+
+long long __ashrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		/* w.s.high = 1..1 or 0..0 */
+		w.s.high =
+		    uu.s.high >> 31;
+		w.s.low = uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}
+EXPORT_SYMBOL(__ashrdi3);
diff --git a/arch/riscv/lib/delay.c b/arch/riscv/lib/delay.c
new file mode 100644
index 000000000000..3c7bf85a0b04
--- /dev/null
+++ b/arch/riscv/lib/delay.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/param.h>
+#include <linux/timex.h>
+#include <linux/export.h>
+
+void __delay(unsigned long cycles)
+{
+	u64 t0 = get_cycles();
+
+	while ((unsigned long)(get_cycles() - t0) < cycles)
+		cpu_relax();
+}
+
+void udelay(unsigned long usecs)
+{
+	u64 ucycles = (u64)usecs * timebase;
+	do_div(ucycles, 1000000U);
+	__delay((unsigned long)ucycles);
+}
+EXPORT_SYMBOL(udelay);
+
+void ndelay(unsigned long nsecs)
+{
+	u64 ncycles = (u64)nsecs * timebase;
+	do_div(ncycles, 1000000000U);
+	__delay((unsigned long)ncycles);
+}
+EXPORT_SYMBOL(ndelay);
diff --git a/arch/riscv/lib/libgcc.h b/arch/riscv/lib/libgcc.h
new file mode 100644
index 000000000000..2d3fa9d87922
--- /dev/null
+++ b/arch/riscv/lib/libgcc.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+extern long long __ashldi3(long long u, word_type b);
+extern long long __ashrdi3(long long u, word_type b);
+extern word_type __cmpdi2(long long a, long long b);
+extern long long __lshrdi3(long long u, word_type b);
+extern long long __muldi3(long long u, long long v);
+extern word_type __ucmpdi2(unsigned long long a, unsigned long long b);
+
+#endif /* __ASM_LIBGCC_H */
diff --git a/arch/riscv/lib/lshrdi3.c b/arch/riscv/lib/lshrdi3.c
new file mode 100644
index 000000000000..ad4e132959f9
--- /dev/null
+++ b/arch/riscv/lib/lshrdi3.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 Darius Rad <darius@bluespec.com>
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/export.h>
+
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.high = 0;
+		w.s.low = (unsigned int) uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = (unsigned int) uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}
+EXPORT_SYMBOL(__lshrdi3);
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
new file mode 100644
index 000000000000..1d789ff57d7d
--- /dev/null
+++ b/arch/riscv/lib/memcpy.S
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memcpy(void *, const void *, size_t) */
+ENTRY(memcpy)
+	move t6, a0  /* Preserve return value */
+
+	/* Defer to byte-oriented copy for small sizes */
+	sltiu a3, a2, 128
+	bnez a3, 4f
+	/* Use word-oriented copy only if low-order bits match */
+	andi a3, t6, SZREG-1
+	andi a4, a1, SZREG-1
+	bne a3, a4, 4f
+
+	beqz a3, 2f  /* Skip if already aligned */
+	/* Round to nearest double word-aligned address
+	   greater than or equal to start address */
+	andi a3, a1, ~(SZREG-1)
+	addi a3, a3, SZREG
+	/* Handle initial misalignment */
+	sub a4, a3, a1
+1:
+	lb a5, 0(a1)
+	addi a1, a1, 1
+	sb a5, 0(t6)
+	addi t6, t6, 1
+	bltu a1, a3, 1b
+	sub a2, a2, a4  /* Update count */
+
+2:
+	andi a4, a2, ~((16*SZREG)-1)
+	beqz a4, 4f
+	add a3, a1, a4
+3:
+	REG_L a4,       0(a1)
+	REG_L a5,   SZREG(a1)
+	REG_L a6, 2*SZREG(a1)
+	REG_L a7, 3*SZREG(a1)
+	REG_L t0, 4*SZREG(a1)
+	REG_L t1, 5*SZREG(a1)
+	REG_L t2, 6*SZREG(a1)
+	REG_L t3, 7*SZREG(a1)
+	REG_L t4, 8*SZREG(a1)
+	REG_L t5, 9*SZREG(a1)
+	REG_S a4,       0(t6)
+	REG_S a5,   SZREG(t6)
+	REG_S a6, 2*SZREG(t6)
+	REG_S a7, 3*SZREG(t6)
+	REG_S t0, 4*SZREG(t6)
+	REG_S t1, 5*SZREG(t6)
+	REG_S t2, 6*SZREG(t6)
+	REG_S t3, 7*SZREG(t6)
+	REG_S t4, 8*SZREG(t6)
+	REG_S t5, 9*SZREG(t6)
+	REG_L a4, 10*SZREG(a1)
+	REG_L a5, 11*SZREG(a1)
+	REG_L a6, 12*SZREG(a1)
+	REG_L a7, 13*SZREG(a1)
+	REG_L t0, 14*SZREG(a1)
+	REG_L t1, 15*SZREG(a1)
+	addi a1, a1, 16*SZREG
+	REG_S a4, 10*SZREG(t6)
+	REG_S a5, 11*SZREG(t6)
+	REG_S a6, 12*SZREG(t6)
+	REG_S a7, 13*SZREG(t6)
+	REG_S t0, 14*SZREG(t6)
+	REG_S t1, 15*SZREG(t6)
+	addi t6, t6, 16*SZREG
+	bltu a1, a3, 3b
+	andi a2, a2, (16*SZREG)-1  /* Update count */
+
+4:
+	/* Handle trailing misalignment */
+	beqz a2, 6f
+	add a3, a1, a2
+5:
+	lb a4, 0(a1)
+	addi a1, a1, 1
+	sb a4, 0(t6)
+	addi t6, t6, 1
+	bltu a1, a3, 5b
+6:
+	ret
+END(memcpy)
diff --git a/arch/riscv/lib/memset.S b/arch/riscv/lib/memset.S
new file mode 100644
index 000000000000..9d5156899232
--- /dev/null
+++ b/arch/riscv/lib/memset.S
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memset(void *, int, size_t) */
+ENTRY(memset)
+	move t0, a0  /* Preserve return value */
+
+	/* Defer to byte-oriented fill for small sizes */
+	sltiu a3, a2, 16
+	bnez a3, 4f
+
+	/* Round to nearest XLEN-aligned address
+	   greater than or equal to start address */
+	addi a3, t0, SZREG-1
+	andi a3, a3, ~(SZREG-1)
+	beq a3, t0, 2f  /* Skip if already aligned */
+	/* Handle initial misalignment */
+	sub a4, a3, t0
+1:
+	sb a1, 0(t0)
+	addi t0, t0, 1
+	bltu t0, a3, 1b
+	sub a2, a2, a4  /* Update count */
+
+2: /* Duff's device with 32 XLEN stores per iteration */
+	/* Broadcast value into all bytes */
+	andi a1, a1, 0xff
+	slli a3, a1, 8
+	or a1, a3, a1
+	slli a3, a1, 16
+	or a1, a3, a1
+#ifdef CONFIG_64BIT
+	slli a3, a1, 32
+	or a1, a3, a1
+#endif
+
+	/* Calculate end address */
+	andi a4, a2, ~(SZREG-1)
+	add a3, t0, a4
+
+	andi a4, a4, 31*SZREG  /* Calculate remainder */
+	beqz a4, 3f            /* Shortcut if no remainder */
+	neg a4, a4
+	addi a4, a4, 32*SZREG  /* Calculate initial offset */
+
+	/* Adjust start address with offset */
+	sub t0, t0, a4
+
+	/* Jump into loop body */
+	/* Assumes 32-bit instruction lengths */
+	la a5, 3f
+#ifdef CONFIG_64BIT
+	srli a4, a4, 1
+#endif
+	add a5, a5, a4
+	jr a5
+3:
+	REG_S a1,        0(t0)
+	REG_S a1,    SZREG(t0)
+	REG_S a1,  2*SZREG(t0)
+	REG_S a1,  3*SZREG(t0)
+	REG_S a1,  4*SZREG(t0)
+	REG_S a1,  5*SZREG(t0)
+	REG_S a1,  6*SZREG(t0)
+	REG_S a1,  7*SZREG(t0)
+	REG_S a1,  8*SZREG(t0)
+	REG_S a1,  9*SZREG(t0)
+	REG_S a1, 10*SZREG(t0)
+	REG_S a1, 11*SZREG(t0)
+	REG_S a1, 12*SZREG(t0)
+	REG_S a1, 13*SZREG(t0)
+	REG_S a1, 14*SZREG(t0)
+	REG_S a1, 15*SZREG(t0)
+	REG_S a1, 16*SZREG(t0)
+	REG_S a1, 17*SZREG(t0)
+	REG_S a1, 18*SZREG(t0)
+	REG_S a1, 19*SZREG(t0)
+	REG_S a1, 20*SZREG(t0)
+	REG_S a1, 21*SZREG(t0)
+	REG_S a1, 22*SZREG(t0)
+	REG_S a1, 23*SZREG(t0)
+	REG_S a1, 24*SZREG(t0)
+	REG_S a1, 25*SZREG(t0)
+	REG_S a1, 26*SZREG(t0)
+	REG_S a1, 27*SZREG(t0)
+	REG_S a1, 28*SZREG(t0)
+	REG_S a1, 29*SZREG(t0)
+	REG_S a1, 30*SZREG(t0)
+	REG_S a1, 31*SZREG(t0)
+	addi t0, t0, 32*SZREG
+	bltu t0, a3, 3b
+	andi a2, a2, SZREG-1  /* Update count */
+
+4:
+	/* Handle trailing misalignment */
+	beqz a2, 6f
+	add a3, t0, a2
+5:
+	sb a1, 0(t0)
+	addi t0, t0, 1
+	bltu t0, a3, 5b
+6:
+	ret
+END(memset)
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
new file mode 100644
index 000000000000..971ae7d86f97
--- /dev/null
+++ b/arch/riscv/lib/uaccess.S
@@ -0,0 +1,125 @@
+#include <linux/linkage.h>
+#include <asm/asm.h>
+#include <asm/csr.h>
+
+	.altmacro
+	.macro fixup op reg addr lbl
+	LOCAL _epc
+_epc:
+	\op \reg, \addr
+	.section __ex_table,"a"
+	.balign SZPTR
+	PTR _epc, \lbl
+	.previous
+	.endm
+
+ENTRY(__copy_user)
+
+#ifdef CONFIG_RV_PUM
+	/* Enable access to user memory */
+	li t6, SR_SUM
+	csrs sstatus, t6
+#endif
+
+	add a3, a1, a2
+	/* Use word-oriented copy only if low-order bits match */
+	andi t0, a0, SZREG-1
+	andi t1, a1, SZREG-1
+	bne t0, t1, 2f
+
+	addi t0, a1, SZREG-1
+	andi t1, a3, ~(SZREG-1)
+	andi t0, t0, ~(SZREG-1)
+	/* a3: terminal address of source region
+	 * t0: lowest XLEN-aligned address in source
+	 * t1: highest XLEN-aligned address in source
+	 */
+	bgeu t0, t1, 2f
+	bltu a1, t0, 4f
+1:
+	fixup REG_L, t2, (a1), 10f
+	fixup REG_S, t2, (a0), 10f
+	addi a1, a1, SZREG
+	addi a0, a0, SZREG
+	bltu a1, t1, 1b
+2:
+	bltu a1, a3, 5f
+
+3:
+#ifdef CONFIG_RV_PUM
+	/* Disable access to user memory */
+	csrc sstatus, t6
+#endif
+	li a0, 0
+	ret
+4: /* Edge case: unalignment */
+	fixup lbu, t2, (a1), 10f
+	fixup sb, t2, (a0), 10f
+	addi a1, a1, 1
+	addi a0, a0, 1
+	bltu a1, t0, 4b
+	j 1b
+5: /* Edge case: remainder */
+	fixup lbu, t2, (a1), 10f
+	fixup sb, t2, (a0), 10f
+	addi a1, a1, 1
+	addi a0, a0, 1
+	bltu a1, a3, 5b
+	j 3b
+ENDPROC(__copy_user)
+
+
+ENTRY(__clear_user)
+
+#ifdef CONFIG_RV_PUM
+	/* Enable access to user memory */
+	li t6, SR_SUM
+	csrs sstatus, t6
+#endif
+
+	add a3, a0, a1
+	addi t0, a0, SZREG-1
+	andi t1, a3, ~(SZREG-1)
+	andi t0, t0, ~(SZREG-1)
+	/* a3: terminal address of target region
+	 * t0: lowest doubleword-aligned address in target region
+	 * t1: highest doubleword-aligned address in target region
+	 */
+	bgeu t0, t1, 2f
+	bltu a0, t0, 4f
+1:
+	fixup REG_S, zero, (a0), 10f
+	addi a0, a0, SZREG
+	bltu a0, t1, 1b
+2:
+	bltu a0, a3, 5f
+
+3:
+#ifdef CONFIG_RV_PUM
+	/* Disable access to user memory */
+	csrc sstatus, t6
+#endif
+	li a0, 0
+	ret
+4: /* Edge case: unalignment */
+	fixup sb, zero, (a0), 10f
+	addi a0, a0, 1
+	bltu a0, t0, 4b
+	j 1b
+5: /* Edge case: remainder */
+	fixup sb, zero, (a0), 10f
+	addi a0, a0, 1
+	bltu a0, a3, 5b
+	j 3b
+ENDPROC(__clear_user)
+
+	.section .fixup,"ax"
+	.balign 4
+10:
+#ifdef CONFIG_RV_PUM
+	/* Disable access to user memory */
+	csrs sstatus, t6
+#endif
+	sub a0, a3, a0
+	ret
+	.previous
-- 
2.13.0

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#1647934 — Re: [PATCH 5/7] RISC-V: arch/riscv/lib

Hi Palmer,

On Tue, May 23, 2017 at 2:41 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>  arch/riscv/lib/Makefile  |   5 ++
>  arch/riscv/lib/ashldi3.c |  42 ++++++++++++++++

At least this one has already two identical copies in arch/score/lib/ashldi3.c
and arch/sh/lib/ashldi3.c. Probably these should be moved to lib/, and built
depending on a new config symbol that is selected on score, sh, and riscv.

Didn't check the others.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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#1648886 — Re: [PATCH 5/7] RISC-V: arch/riscv/lib

On Tue, 23 May 2017 03:47:34 PDT (-0700), geert@linux-m68k.org wrote:
> Hi Palmer,
>
> On Tue, May 23, 2017 at 2:41 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>  arch/riscv/lib/Makefile  |   5 ++
>>  arch/riscv/lib/ashldi3.c |  42 ++++++++++++++++
>
> At least this one has already two identical copies in arch/score/lib/ashldi3.c
> and arch/sh/lib/ashldi3.c. Probably these should be moved to lib/, and built
> depending on a new config symbol that is selected on score, sh, and riscv.
>
> Didn't check the others.

Thanks.  It looks like there's actually a lot of these on many architectures.
I have another patch set to correct all of these that you're To'd on, I'll just
pick up the first patch in the set for v2

https://lkml.org/lkml/2017/5/23/1280

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#1647953 — Re: [PATCH 5/7] RISC-V: arch/riscv/lib

On Tue, May 23, 2017 at 2:41 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> new file mode 100644
> index 000000000000..f644e582f4b8
> --- /dev/null
> +++ b/arch/riscv/lib/Makefile

> +
> +void __delay(unsigned long cycles)
> +{
> +       u64 t0 = get_cycles();
> +
> +       while ((unsigned long)(get_cycles() - t0) < cycles)
> +               cpu_relax();
> +}
> +
> +void udelay(unsigned long usecs)
> +{
> +       u64 ucycles = (u64)usecs * timebase;
> +       do_div(ucycles, 1000000U);
> +       __delay((unsigned long)ucycles);
> +}
> +EXPORT_SYMBOL(udelay);
> +
> +void ndelay(unsigned long nsecs)
> +{
> +       u64 ncycles = (u64)nsecs * timebase;
> +       do_div(ncycles, 1000000000U);
> +       __delay((unsigned long)ncycles);
> +}

I'd be slightly worried about a global 'timebase' identifier that
might conflict with a variable in some random driver.

Also, it would be good to replace the multiply+div64
with a single multiplication here, see how x86 and arm do it
(for the tsc/__timer_delay case).

      Arnd

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#1647530 — [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

---
 arch/riscv/.gitignore                |  35 ++++
 arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
 arch/riscv/Makefile                  |  64 ++++++++
 arch/riscv/configs/riscv32_spike     |  47 ++++++
 arch/riscv/configs/riscv64_freedom-u |  52 ++++++
 arch/riscv/configs/riscv64_qemu      |  64 ++++++++
 arch/riscv/configs/riscv64_spike     |  45 ++++++
 7 files changed, 607 insertions(+)
 create mode 100644 arch/riscv/.gitignore
 create mode 100644 arch/riscv/Kconfig
 create mode 100644 arch/riscv/Makefile
 create mode 100644 arch/riscv/configs/riscv32_spike
 create mode 100644 arch/riscv/configs/riscv64_freedom-u
 create mode 100644 arch/riscv/configs/riscv64_qemu
 create mode 100644 arch/riscv/configs/riscv64_spike

diff --git a/arch/riscv/.gitignore b/arch/riscv/.gitignore
new file mode 100644
index 000000000000..376d06eb5d52
--- /dev/null
+++ b/arch/riscv/.gitignore
@@ -0,0 +1,35 @@
+# Now un-ignore all files.
+!*
+
+# But then re-ignore the files listed in the Linux .gitignore
+# Normal rules
+#
+.*
+*.o
+*.o.*
+*.a
+*.s
+*.ko
+*.so
+*.so.dbg
+*.mod.c
+*.i
+*.lst
+*.symtypes
+*.order
+modules.builtin
+*.elf
+*.bin
+*.gz
+*.bz2
+*.lzma
+*.xz
+*.lzo
+*.patch
+*.gcno
+
+include/generated
+kernel/vmlinux.lds
+
+# Then reinclude .gitignore.
+!.gitignore
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
new file mode 100644
index 000000000000..510ead1d3343
--- /dev/null
+++ b/arch/riscv/Kconfig
@@ -0,0 +1,300 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config RISCV
+	def_bool y
+	select OF
+	select OF_EARLY_FLATTREE
+	select OF_IRQ
+	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
+	select ARCH_WANT_FRAME_POINTERS
+	select CLONE_BACKWARDS
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_CPU_DEVICES
+	select GENERIC_IRQ_SHOW
+	select GENERIC_PCI_IOMAP
+	select GENERIC_STRNCPY_FROM_USER
+	select GENERIC_STRNLEN_USER
+	select GENERIC_SMP_IDLE_THREAD
+	select GENERIC_ATOMIC64 if !64BIT || !RV_ATOMIC
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	select HAVE_MEMBLOCK
+	select HAVE_DMA_API_DEBUG
+	select HAVE_DMA_CONTIGUOUS
+	select HAVE_GENERIC_DMA_COHERENT
+	select IRQ_DOMAIN
+	select NO_BOOTMEM
+	select RV_ATOMIC if SMP
+	select RV_SYSRISCV_ATOMIC if !RV_ATOMIC
+	select SPARSE_IRQ
+	select SYSCTL_EXCEPTION_TRACE
+	select HAVE_ARCH_TRACEHOOK
+	select MODULES_USE_ELF_RELA if MODULES
+
+config MMU
+	def_bool y
+
+# even on 32-bit, physical (and DMA) addresses are > 32-bits
+config ARCH_PHYS_ADDR_T_64BIT
+	def_bool y
+
+config ARCH_DMA_ADDR_T_64BIT
+	def_bool y
+
+config STACKTRACE_SUPPORT
+	def_bool y
+
+config RWSEM_GENERIC_SPINLOCK
+	def_bool y
+
+config GENERIC_BUG
+	def_bool y
+	depends on BUG
+	select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
+
+config GENERIC_BUG_RELATIVE_POINTERS
+	bool
+
+config GENERIC_CALIBRATE_DELAY
+	def_bool y
+
+config GENERIC_CSUM
+	def_bool y
+
+config GENERIC_HWEIGHT
+	def_bool y
+
+config PGTABLE_LEVELS
+	int
+	default 3 if 64BIT
+	default 2
+
+config HAVE_KPROBES
+	def_bool n
+
+config DMA_NOOP_OPS
+	def_bool y
+
+menu "Platform type"
+
+config SMP
+	bool "Symmetric Multi-Processing"
+	help
+	  This enables support for systems with more than one CPU.  If
+	  you say N here, the kernel will run on single and
+	  multiprocessor machines, but will use only one CPU of a
+	  multiprocessor machine. If you say Y here, the kernel will run
+	  on many, but not all, single processor machines. On a single
+	  processor machine, the kernel will run faster if you say N
+	  here.
+
+	  If you don't know what to do here, say N.
+
+config NR_CPUS
+	int "Maximum number of CPUs (2-32)"
+	range 2 32
+	depends on SMP
+	default "8"
+
+choice
+	prompt "CPU selection"
+	default CPU_RV_GENERIC
+
+config CPU_RV_GENERIC
+	bool "Generic RISC-V"
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_SUPPORTS_64BIT_KERNEL
+
+endchoice
+
+config PLIC
+	bool "Platform-Level Interrupt Controller"
+	default y
+	help
+	   This enables support for the PLIC chip found in standard RISC-V
+	   systems. The PLIC is the top-most interrupt controller found in
+	   the system, connected directly to the core complex. All other
+	   interrupt sources (MSI, GPIO, etc) are subordinate to the PLIC.
+
+	   If you don't know what to do here, say Y.
+
+config CPU_SUPPORTS_32BIT_KERNEL
+	bool
+config CPU_SUPPORTS_64BIT_KERNEL
+	bool
+
+config SBI_CONSOLE
+	tristate "SBI console support"
+	select TTY
+	default y
+
+config RVC
+	bool "Use compressed instructions (RV32C or RV64C)"
+	default n
+
+config RV_ATOMIC
+	bool "Use atomic memory instructions (RV32A or RV64A)"
+	default y
+
+config RV_SYSRISCV_ATOMIC
+	bool "Include support for atomic operation syscalls"
+	default n
+	help
+	  If atomic memory instructions are present, i.e.,
+	  CONFIG_RV_ATOMIC, this includes support for the syscall that
+	  provides atomic accesses.  This is only useful to run
+	  binaries that require atomic access but were compiled with
+	  -mno-atomic.
+
+	  If CONFIG_RV_ATOMIC is unset, this option is mandatory.
+
+config RV_PUM
+	def_bool y
+	prompt "Protect User Memory" if EXPERT
+	---help---
+	  Protect User Memory (PUM) prevents the kernel from inadvertently
+	  accessing user-space memory.  There is a small performance cost
+	  and kernel size increase if this is enabled.
+
+	  If unsure, say Y.
+
+endmenu
+
+menu "Kernel type"
+
+choice
+	prompt "Kernel code model"
+	default 64BIT
+
+config 32BIT
+	bool "32-bit kernel"
+	depends on CPU_SUPPORTS_32BIT_KERNEL
+	help
+	  Select this option to build a 32-bit kernel.
+
+config 64BIT
+	bool "64-bit kernel"
+	depends on CPU_SUPPORTS_64BIT_KERNEL
+	help
+	  Select this option to build a 64-bit kernel.
+
+endchoice
+
+source "mm/Kconfig"
+
+source "kernel/Kconfig.preempt"
+
+source "kernel/Kconfig.hz"
+
+endmenu
+
+menu "Bus support"
+
+config PCI
+	bool "PCI support"
+	select PCI_MSI
+	help
+	  This feature enables support for PCI bus system. If you say Y
+	  here, the kernel will include drivers and infrastructure code
+	  to support PCI bus devices.
+
+config PCI_DOMAINS
+	def_bool PCI
+
+config PCI_DOMAINS_GENERIC
+	def_bool PCI
+
+config PCI_SYSCALL
+	def_bool PCI
+
+source "drivers/pci/Kconfig"
+
+endmenu
+
+source "init/Kconfig"
+
+source "kernel/Kconfig.freezer"
+
+menu "Executable file formats"
+
+source "fs/Kconfig.binfmt"
+
+endmenu
+
+menu "Power management options"
+
+source kernel/power/Kconfig
+
+endmenu
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+
+config CMDLINE_BOOL
+	bool "Built-in kernel command line"
+	default n
+	help
+	  For most platforms, it is firmware or second stage bootloader
+	  that by default specifies the kernel command line options.
+	  However, it might be necessary or advantageous to either override
+	  the default kernel command line or add a few extra options to it.
+	  For such cases, this option allows hardcoding command line options
+	  directly into the kernel.
+
+	  For that, choose 'Y' here and fill in the extra boot parameters
+	  in CONFIG_CMDLINE.
+
+	  The built-in options will be concatenated to the default command
+	  line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
+	  command line will be ignored and replaced by the built-in string.
+
+config CMDLINE
+	string "Built-in kernel command string"
+	depends on CMDLINE_BOOL
+	default ""
+	help
+	  Supply command-line options at build time by entering them here.
+
+config CMDLINE_OVERRIDE
+	bool "Built-in command line overrides bootloader arguments"
+	default n
+	depends on CMDLINE_BOOL
+	help
+	  Set this option to 'Y' to have the kernel ignore the bootloader
+	  or firmware command line.  Instead, the built-in command line
+	  will be used exclusively.
+
+config EARLY_PRINTK
+	bool "Early printk"
+	default n
+	help
+	  This option enables special console drivers which allow the kernel
+	  to print messages very early in the bootup process.
+
+	  This is useful for kernel debugging when your machine crashes very
+	  early before the console code is initialized. For normal operation
+	  it is not recommended because it looks ugly and doesn't cooperate
+	  with klogd/syslogd or the X server. You should normally N here,
+	  unless you want to debug such a crash.
+
+
+source "lib/Kconfig.debug"
+
+config CMDLINE_BOOL
+	bool
+endmenu
+
+source "security/Kconfig"
+
+source "crypto/Kconfig"
+
+source "lib/Kconfig"
+
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
new file mode 100644
index 000000000000..07ef200e0675
--- /dev/null
+++ b/arch/riscv/Makefile
@@ -0,0 +1,64 @@
+# This file is included by the global makefile so that you can add your own
+# architecture-specific flags and dependencies. Remember to do have actions
+# for "archclean" and "archdep" for cleaning up and making dependencies for
+# this architecture
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+
+LDFLAGS         :=
+OBJCOPYFLAGS    := -O binary
+LDFLAGS_vmlinux :=
+KBUILD_AFLAGS_MODULE += -fPIC
+KBUILD_CFLAGS_MODULE += -fPIC
+
+ifeq ($(ARCH),riscv)
+	KBUILD_DEFCONFIG = riscv64_spike
+else
+	KBUILD_DEFCONFIG = $(ARCH)_spike
+endif
+
+export BITS
+ifeq ($(CONFIG_64BIT),y)
+	BITS := 64
+	UTS_MACHINE := riscv64
+
+	KBUILD_CFLAGS += -mabi=lp64
+	KBUILD_AFLAGS += -mabi=lp64
+	KBUILD_MARCH = rv64im
+	LDFLAGS += -melf64lriscv
+else
+	BITS := 32
+	UTS_MACHINE := riscv32
+
+	KBUILD_CFLAGS += -mabi=ilp32
+	KBUILD_AFLAGS += -mabi=ilp32
+	KBUILD_MARCH = rv32im
+	LDFLAGS += -melf32lriscv
+endif
+
+ifeq ($(CONFIG_RV_ATOMIC),y)
+	KBUILD_RV_ATOMIC = a
+endif
+
+KBUILD_CFLAGS += -Wall
+
+ifeq ($(CONFIG_RVC),y)
+	KBUILD_RVC = c
+endif
+
+KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_RV_ATOMIC)fd$(KBUILD_RVC)
+
+KBUILD_CFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_RV_ATOMIC)$(KBUILD_RVC)
+KBUILD_CFLAGS += -mno-save-restore
+KBUILD_CFLAGS += -mstrict-align
+
+head-y := arch/riscv/kernel/head.o
+
+core-y += arch/riscv/kernel/ arch/riscv/mm/
+
+libs-y += arch/riscv/lib/
+
+all: vmlinux
diff --git a/arch/riscv/configs/riscv32_spike b/arch/riscv/configs/riscv32_spike
new file mode 100644
index 000000000000..c224f7dcb4da
--- /dev/null
+++ b/arch/riscv/configs/riscv32_spike
@@ -0,0 +1,47 @@
+CONFIG_64BIT=n
+CONFIG_32BIT=y
+CONFIG_PCI=y
+CONFIG_DEFAULT_HOSTNAME="ucbvax"
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+# CONFIG_FHANDLE is not set
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+# CONFIG_SYSFS is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/riscv/configs/riscv64_freedom-u b/arch/riscv/configs/riscv64_freedom-u
new file mode 100644
index 000000000000..519cb8219b40
--- /dev/null
+++ b/arch/riscv/configs/riscv64_freedom-u
@@ -0,0 +1,52 @@
+CONFIG_CROSS_COMPILE="riscv64-unknown-linux-gnu-"
+CONFIG_DEFAULT_HOSTNAME="ucbvax"
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+# CONFIG_FHANDLE is not set
+CONFIG_NAMESPACES=y
+# CONFIG_SGETMASK_SYSCALL is not set
+CONFIG_EMBEDDED=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+CONFIG_PCI_MSI=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_OF=y
+# CONFIG_BLK_DEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+# CONFIG_SYSFS is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/riscv/configs/riscv64_qemu b/arch/riscv/configs/riscv64_qemu
new file mode 100644
index 000000000000..4b1190ad2676
--- /dev/null
+++ b/arch/riscv/configs/riscv64_qemu
@@ -0,0 +1,64 @@
+# CONFIG_COMPACTION is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_HZ_100=y
+# CONFIG_CROSS_COMPILE is not set
+CONFIG_DEFAULT_HOSTNAME="ucbvax"
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_VIRTIO=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
+# CONFIG_ETHERNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT4_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="virtio_mmio.device=0x200@0x400:1 virtio_mmio.device=0x200@0x600:2 virtio_mmio.device=0x200@0x800:3 lpj=100000"
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/riscv/configs/riscv64_spike b/arch/riscv/configs/riscv64_spike
new file mode 100644
index 000000000000..a48e92cba88e
--- /dev/null
+++ b/arch/riscv/configs/riscv64_spike
@@ -0,0 +1,45 @@
+CONFIG_PCI=y
+CONFIG_DEFAULT_HOSTNAME="ucbvax"
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+# CONFIG_FHANDLE is not set
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+# CONFIG_SYSFS is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_CRYPTO_HW is not set
-- 
2.13.0

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#1647553 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

Hi,


On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> ---
>  arch/riscv/.gitignore                |  35 ++++
>  arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
>  arch/riscv/Makefile                  |  64 ++++++++
>  arch/riscv/configs/riscv32_spike     |  47 ++++++
>  arch/riscv/configs/riscv64_freedom-u |  52 ++++++
>  arch/riscv/configs/riscv64_qemu      |  64 ++++++++
>  arch/riscv/configs/riscv64_spike     |  45 ++++++
>  7 files changed, 607 insertions(+)
>  create mode 100644 arch/riscv/.gitignore
>  create mode 100644 arch/riscv/Kconfig
>  create mode 100644 arch/riscv/Makefile
>  create mode 100644 arch/riscv/configs/riscv32_spike
>  create mode 100644 arch/riscv/configs/riscv64_freedom-u
>  create mode 100644 arch/riscv/configs/riscv64_qemu
>  create mode 100644 arch/riscv/configs/riscv64_spike

Nearly all other platforms have _defconfig in the config names. It
might get a bit excessive to prepend riscv{32,64} to all of them
though. Most other platforms have shortened it to, for example,
spike_defconfig, spike64_defconfig, qemu_defconfig,
freedom-u_defconfig.

Not going to argue too much about the color of the shed here, but
using the _defconfig naming is recommended.

>
> diff --git a/arch/riscv/.gitignore b/arch/riscv/.gitignore
> new file mode 100644
> index 000000000000..376d06eb5d52
> --- /dev/null
> +++ b/arch/riscv/.gitignore
> @@ -0,0 +1,35 @@
> +# Now un-ignore all files.
> +!*
> +
> +# But then re-ignore the files listed in the Linux .gitignore
> +# Normal rules
> +#
> +.*
> +*.o
> +*.o.*
> +*.a
> +*.s
> +*.ko
> +*.so
> +*.so.dbg
> +*.mod.c
> +*.i
> +*.lst
> +*.symtypes
> +*.order
> +modules.builtin
> +*.elf
> +*.bin
> +*.gz
> +*.bz2
> +*.lzma
> +*.xz
> +*.lzo
> +*.patch
> +*.gcno

I don't think you need to do any of this, just inherit the global one
(by not having one here)?

> +
> +include/generated

This is already covered by the global .gitignore.

> +kernel/vmlinux.lds

And if needed this should be added to the arch/riscv/kernel/.gitignore
file instead.


> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> new file mode 100644
> index 000000000000..510ead1d3343
> --- /dev/null
> +++ b/arch/riscv/Kconfig
> @@ -0,0 +1,300 @@
> +#
> +# For a description of the syntax of this configuration file,
> +# see Documentation/kbuild/kconfig-language.txt.
> +#
> +
> +config RISCV
> +       def_bool y
> +       select OF
> +       select OF_EARLY_FLATTREE
> +       select OF_IRQ
> +       select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
> +       select ARCH_WANT_FRAME_POINTERS
> +       select CLONE_BACKWARDS
> +       select COMMON_CLK
> +       select GENERIC_CLOCKEVENTS
> +       select GENERIC_CPU_DEVICES
> +       select GENERIC_IRQ_SHOW
> +       select GENERIC_PCI_IOMAP
> +       select GENERIC_STRNCPY_FROM_USER
> +       select GENERIC_STRNLEN_USER
> +       select GENERIC_SMP_IDLE_THREAD
> +       select GENERIC_ATOMIC64 if !64BIT || !RV_ATOMIC
> +       select ARCH_WANT_OPTIONAL_GPIOLIB
> +       select HAVE_MEMBLOCK
> +       select HAVE_DMA_API_DEBUG
> +       select HAVE_DMA_CONTIGUOUS
> +       select HAVE_GENERIC_DMA_COHERENT
> +       select IRQ_DOMAIN
> +       select NO_BOOTMEM
> +       select RV_ATOMIC if SMP
> +       select RV_SYSRISCV_ATOMIC if !RV_ATOMIC
> +       select SPARSE_IRQ
> +       select SYSCTL_EXCEPTION_TRACE
> +       select HAVE_ARCH_TRACEHOOK
> +       select MODULES_USE_ELF_RELA if MODULES
> +
> +config MMU
> +       def_bool y
> +
> +# even on 32-bit, physical (and DMA) addresses are > 32-bits
> +config ARCH_PHYS_ADDR_T_64BIT
> +       def_bool y
> +
> +config ARCH_DMA_ADDR_T_64BIT
> +       def_bool y
> +
> +config STACKTRACE_SUPPORT
> +       def_bool y
> +
> +config RWSEM_GENERIC_SPINLOCK
> +       def_bool y
> +
> +config GENERIC_BUG
> +       def_bool y
> +       depends on BUG
> +       select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
> +
> +config GENERIC_BUG_RELATIVE_POINTERS
> +       bool
> +
> +config GENERIC_CALIBRATE_DELAY
> +       def_bool y
> +
> +config GENERIC_CSUM
> +       def_bool y
> +
> +config GENERIC_HWEIGHT
> +       def_bool y
> +
> +config PGTABLE_LEVELS
> +       int
> +       default 3 if 64BIT
> +       default 2
> +
> +config HAVE_KPROBES
> +       def_bool n
> +
> +config DMA_NOOP_OPS
> +       def_bool y
> +
> +menu "Platform type"
> +
> +config SMP
> +       bool "Symmetric Multi-Processing"
> +       help
> +         This enables support for systems with more than one CPU.  If
> +         you say N here, the kernel will run on single and
> +         multiprocessor machines, but will use only one CPU of a
> +         multiprocessor machine. If you say Y here, the kernel will run
> +         on many, but not all, single processor machines. On a single
> +         processor machine, the kernel will run faster if you say N
> +         here.
> +
> +         If you don't know what to do here, say N.
> +
> +config NR_CPUS
> +       int "Maximum number of CPUs (2-32)"
> +       range 2 32
> +       depends on SMP
> +       default "8"
> +
> +choice
> +       prompt "CPU selection"
> +       default CPU_RV_GENERIC
> +
> +config CPU_RV_GENERIC
> +       bool "Generic RISC-V"
> +       select CPU_SUPPORTS_32BIT_KERNEL
> +       select CPU_SUPPORTS_64BIT_KERNEL

Is this even needed at this point? If the only CPU you can pick
supports this, you might as well not make it an option (CPU_RV_GENERIC
that is), and just make CPU_SUPPORTS_{32,64}BIT_KERNEL 'def_bool y'
for now.

> +
> +endchoice
> +
> +config PLIC
> +       bool "Platform-Level Interrupt Controller"
> +       default y
> +       help
> +          This enables support for the PLIC chip found in standard RISC-V
> +          systems. The PLIC is the top-most interrupt controller found in
> +          the system, connected directly to the core complex. All other
> +          interrupt sources (MSI, GPIO, etc) are subordinate to the PLIC.
> +
> +          If you don't know what to do here, say Y.
> +
> +config CPU_SUPPORTS_32BIT_KERNEL
> +       bool
> +config CPU_SUPPORTS_64BIT_KERNEL
> +       bool
> +
> +config SBI_CONSOLE
> +       tristate "SBI console support"
> +       select TTY
> +       default y

Usually you end up having a DRIVER_FOO and DRIVER_FOO_CONSOLE option
to enable registering it as console.

Also, unless there's strong reason to keep it under arch/, it should
probably go under drivers/tty/.

> +config RVC
> +       bool "Use compressed instructions (RV32C or RV64C)"
> +       default n

What does "use" here mean? Use during build, or allow userspace to use them?

> +
> +config RV_ATOMIC
> +       bool "Use atomic memory instructions (RV32A or RV64A)"
> +       default y

Same for this.

> +config RV_SYSRISCV_ATOMIC
> +       bool "Include support for atomic operation syscalls"
> +       default n
> +       help
> +         If atomic memory instructions are present, i.e.,
> +         CONFIG_RV_ATOMIC, this includes support for the syscall that
> +         provides atomic accesses.  This is only useful to run
> +         binaries that require atomic access but were compiled with
> +         -mno-atomic.
> +
> +         If CONFIG_RV_ATOMIC is unset, this option is mandatory.

If it's mandatory then Kconfig language should make it so.

> +config RV_PUM
> +       def_bool y
> +       prompt "Protect User Memory" if EXPERT
> +       ---help---
> +         Protect User Memory (PUM) prevents the kernel from inadvertently
> +         accessing user-space memory.  There is a small performance cost
> +         and kernel size increase if this is enabled.
> +
> +         If unsure, say Y.
> +
> +endmenu
> +
> +menu "Kernel type"
> +
> +choice
> +       prompt "Kernel code model"
> +       default 64BIT
> +
> +config 32BIT
> +       bool "32-bit kernel"
> +       depends on CPU_SUPPORTS_32BIT_KERNEL
> +       help
> +         Select this option to build a 32-bit kernel.
> +
> +config 64BIT
> +       bool "64-bit kernel"
> +       depends on CPU_SUPPORTS_64BIT_KERNEL
> +       help
> +         Select this option to build a 64-bit kernel.
> +
> +endchoice
> +
[...]


-Olof

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#1647561 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On 05/22/17 18:27, Olof Johansson wrote:
> Hi,
> 
> 
> On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> ---
>>  arch/riscv/.gitignore                |  35 ++++
>>  arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
>>  arch/riscv/Makefile                  |  64 ++++++++
>>  arch/riscv/configs/riscv32_spike     |  47 ++++++
>>  arch/riscv/configs/riscv64_freedom-u |  52 ++++++
>>  arch/riscv/configs/riscv64_qemu      |  64 ++++++++
>>  arch/riscv/configs/riscv64_spike     |  45 ++++++
>>  7 files changed, 607 insertions(+)
>>  create mode 100644 arch/riscv/.gitignore
>>  create mode 100644 arch/riscv/Kconfig
>>  create mode 100644 arch/riscv/Makefile
>>  create mode 100644 arch/riscv/configs/riscv32_spike
>>  create mode 100644 arch/riscv/configs/riscv64_freedom-u
>>  create mode 100644 arch/riscv/configs/riscv64_qemu
>>  create mode 100644 arch/riscv/configs/riscv64_spike
> 
> Nearly all other platforms have _defconfig in the config names. It
> might get a bit excessive to prepend riscv{32,64} to all of them
> though. Most other platforms have shortened it to, for example,
> spike_defconfig, spike64_defconfig, qemu_defconfig,
> freedom-u_defconfig.
> 
> Not going to argue too much about the color of the shed here, but
> using the _defconfig naming is recommended.

well, the top-level Makefile looks for "make *config" to indicate that
there is a config-command in progress (or in process), so they usually
have to end in the string "config".

Have these been tested?


-- 
~Randy

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#1647625 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On Mon, 22 May 2017 18:31:08 PDT (-0700), rdunlap@infradead.org wrote:
> On 05/22/17 18:27, Olof Johansson wrote:
>> Hi,
>>
>>
>> On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>> ---
>>>  arch/riscv/.gitignore                |  35 ++++
>>>  arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
>>>  arch/riscv/Makefile                  |  64 ++++++++
>>>  arch/riscv/configs/riscv32_spike     |  47 ++++++
>>>  arch/riscv/configs/riscv64_freedom-u |  52 ++++++
>>>  arch/riscv/configs/riscv64_qemu      |  64 ++++++++
>>>  arch/riscv/configs/riscv64_spike     |  45 ++++++
>>>  7 files changed, 607 insertions(+)
>>>  create mode 100644 arch/riscv/.gitignore
>>>  create mode 100644 arch/riscv/Kconfig
>>>  create mode 100644 arch/riscv/Makefile
>>>  create mode 100644 arch/riscv/configs/riscv32_spike
>>>  create mode 100644 arch/riscv/configs/riscv64_freedom-u
>>>  create mode 100644 arch/riscv/configs/riscv64_qemu
>>>  create mode 100644 arch/riscv/configs/riscv64_spike
>>
>> Nearly all other platforms have _defconfig in the config names. It
>> might get a bit excessive to prepend riscv{32,64} to all of them
>> though. Most other platforms have shortened it to, for example,
>> spike_defconfig, spike64_defconfig, qemu_defconfig,
>> freedom-u_defconfig.
>>
>> Not going to argue too much about the color of the shed here, but
>> using the _defconfig naming is recommended.
>
> well, the top-level Makefile looks for "make *config" to indicate that
> there is a config-command in progress (or in process), so they usually
> have to end in the string "config".
>
> Have these been tested?

Ah, that's much better -- I've just been copying them to .config :).  I've
already renamed them to things that end in defconfig.

Thanks!

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#1647628 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On Mon, 22 May 2017 18:27:21 PDT (-0700), olof@lixom.net wrote:
> Hi,
>
>
> On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> ---
>>  arch/riscv/.gitignore                |  35 ++++
>>  arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
>>  arch/riscv/Makefile                  |  64 ++++++++
>>  arch/riscv/configs/riscv32_spike     |  47 ++++++
>>  arch/riscv/configs/riscv64_freedom-u |  52 ++++++
>>  arch/riscv/configs/riscv64_qemu      |  64 ++++++++
>>  arch/riscv/configs/riscv64_spike     |  45 ++++++
>>  7 files changed, 607 insertions(+)
>>  create mode 100644 arch/riscv/.gitignore
>>  create mode 100644 arch/riscv/Kconfig
>>  create mode 100644 arch/riscv/Makefile
>>  create mode 100644 arch/riscv/configs/riscv32_spike
>>  create mode 100644 arch/riscv/configs/riscv64_freedom-u
>>  create mode 100644 arch/riscv/configs/riscv64_qemu
>>  create mode 100644 arch/riscv/configs/riscv64_spike
>
> Nearly all other platforms have _defconfig in the config names. It
> might get a bit excessive to prepend riscv{32,64} to all of them
> though. Most other platforms have shortened it to, for example,
> spike_defconfig, spike64_defconfig, qemu_defconfig,
> freedom-u_defconfig.
>
> Not going to argue too much about the color of the shed here, but
> using the _defconfig naming is recommended.

Works for me <https://github.com/riscv/riscv-linux/commit/b1165397ba6cb54f23910537c4bf4c3488ef9aad>

I'll squash all the CR comments into a v2.

>
>>
>> diff --git a/arch/riscv/.gitignore b/arch/riscv/.gitignore
>> new file mode 100644
>> index 000000000000..376d06eb5d52
>> --- /dev/null
>> +++ b/arch/riscv/.gitignore
>> @@ -0,0 +1,35 @@
>> +# Now un-ignore all files.
>> +!*
>> +
>> +# But then re-ignore the files listed in the Linux .gitignore
>> +# Normal rules
>> +#
>> +.*
>> +*.o
>> +*.o.*
>> +*.a
>> +*.s
>> +*.ko
>> +*.so
>> +*.so.dbg
>> +*.mod.c
>> +*.i
>> +*.lst
>> +*.symtypes
>> +*.order
>> +modules.builtin
>> +*.elf
>> +*.bin
>> +*.gz
>> +*.bz2
>> +*.lzma
>> +*.xz
>> +*.lzo
>> +*.patch
>> +*.gcno
>
> I don't think you need to do any of this, just inherit the global one
> (by not having one here)?

Sorry, that's a holdover from how we used to manage our out-of-tree port and
can just be deleted.

  https://github.com/riscv/riscv-linux/commit/68032fb592297331a2f2caf246968da7b70373fe

>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> new file mode 100644
>> index 000000000000..510ead1d3343
>> --- /dev/null
>> +++ b/arch/riscv/Kconfig
>> +config CPU_RV_GENERIC
>> +       bool "Generic RISC-V"
>> +       select CPU_SUPPORTS_32BIT_KERNEL
>> +       select CPU_SUPPORTS_64BIT_KERNEL
>
> Is this even needed at this point? If the only CPU you can pick
> supports this, you might as well not make it an option (CPU_RV_GENERIC
> that is), and just make CPU_SUPPORTS_{32,64}BIT_KERNEL 'def_bool y'
> for now.

I think this is actually broken in the opposite direction: we only support
32-bit kernels on RV32 and 64-bit kernels on RV64, not both at the same time.
I don't really think it makes sense to build a kernel that supports both 32-bit
and 64-bit on RISC-V (as they're different base ISAs), so I think it'd be
better to just have a "base ISA" configuration.

  https://github.com/riscv/riscv-linux/commit/695d428d65bf6fe1382d34393e9d07f40b74e1b2

We'll think on this a bit more and get something saner.

>> +config SBI_CONSOLE
>> +       tristate "SBI console support"
>> +       select TTY
>> +       default y
>
> Usually you end up having a DRIVER_FOO and DRIVER_FOO_CONSOLE option
> to enable registering it as console.
>
> Also, unless there's strong reason to keep it under arch/, it should
> probably go under drivers/tty/.

In this case "SBI" is the "Supervisor Binary Interface".  This is a set of
routines that are provided by the platform for OS use that do things like
writing to the boot console or TLB shootdowns.  The SBI is part of the RISC-V
ISA, so there isn't a config option for turning it off.  SBI_CONSOLE
enables/disables the SBI's console support, so I think this option is sane.

It's in arch/riscv because the SBI is part of the RISC-V ISA -- essentially
there's special SBI instructions that mean "write some register to the console"
(there's some implementation tricks behind this, so it's really just a
specification).  That said, I'm fine moving this to drivers.

>> +config RVC
>> +       bool "Use compressed instructions (RV32C or RV64C)"
>> +       default n
>
> What does "use" here mean? Use during build, or allow userspace to use them?
>
>> +
>> +config RV_ATOMIC
>> +       bool "Use atomic memory instructions (RV32A or RV64A)"
>> +       default y
>
> Same for this.

These mean "tell the compiler that it can emit these instructions when building
Linux".  Userspace applications can still use these instructions either way.
How does "Emit compressed instructions when building Linux" sound?

  https://github.com/riscv/riscv-linux/commit/d6e65bd8b7dcfa72578d62e5eb367f680b55f5a8

>
>> +config RV_SYSRISCV_ATOMIC
>> +       bool "Include support for atomic operation syscalls"
>> +       default n
>> +       help
>> +         If atomic memory instructions are present, i.e.,
>> +         CONFIG_RV_ATOMIC, this includes support for the syscall that
>> +         provides atomic accesses.  This is only useful to run
>> +         binaries that require atomic access but were compiled with
>> +         -mno-atomic.
>> +
>> +         If CONFIG_RV_ATOMIC is unset, this option is mandatory.
>
> If it's mandatory then Kconfig language should make it so.

I'm not sure what you mean by this.  We have

  config RISCV
  	...
  	select RV_SYSRISCV_ATOMIC if !RV_ATOMIC

Should this constraint just live within "config RV_SYSRISCV_ATOMIC"?  It seems
cleaner to have the constraints next to the config definitions.

Thanks!

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#1647638 — Re: [patches] Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On Mon, May 22, 2017 at 9:49 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> On Mon, 22 May 2017 18:27:21 PDT (-0700), olof@lixom.net wrote:
>> Hi,
>>
>>
>> On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>> ---
>>>  arch/riscv/.gitignore                |  35 ++++
>>>  arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
>>>  arch/riscv/Makefile                  |  64 ++++++++
>>>  arch/riscv/configs/riscv32_spike     |  47 ++++++
>>>  arch/riscv/configs/riscv64_freedom-u |  52 ++++++
>>>  arch/riscv/configs/riscv64_qemu      |  64 ++++++++
>>>  arch/riscv/configs/riscv64_spike     |  45 ++++++
>>>  7 files changed, 607 insertions(+)
>>>  create mode 100644 arch/riscv/.gitignore
>>>  create mode 100644 arch/riscv/Kconfig
>>>  create mode 100644 arch/riscv/Makefile
>>>  create mode 100644 arch/riscv/configs/riscv32_spike
>>>  create mode 100644 arch/riscv/configs/riscv64_freedom-u
>>>  create mode 100644 arch/riscv/configs/riscv64_qemu
>>>  create mode 100644 arch/riscv/configs/riscv64_spike
>>
>> Nearly all other platforms have _defconfig in the config names. It
>> might get a bit excessive to prepend riscv{32,64} to all of them
>> though. Most other platforms have shortened it to, for example,
>> spike_defconfig, spike64_defconfig, qemu_defconfig,
>> freedom-u_defconfig.
>>
>> Not going to argue too much about the color of the shed here, but
>> using the _defconfig naming is recommended.
>
> Works for me <https://github.com/riscv/riscv-linux/commit/b1165397ba6cb54f23910537c4bf4c3488ef9aad>
>
> I'll squash all the CR comments into a v2.
>
>>
>>>
>>> diff --git a/arch/riscv/.gitignore b/arch/riscv/.gitignore
>>> new file mode 100644
>>> index 000000000000..376d06eb5d52
>>> --- /dev/null
>>> +++ b/arch/riscv/.gitignore
>>> @@ -0,0 +1,35 @@
>>> +# Now un-ignore all files.
>>> +!*
>>> +
>>> +# But then re-ignore the files listed in the Linux .gitignore
>>> +# Normal rules
>>> +#
>>> +.*
>>> +*.o
>>> +*.o.*
>>> +*.a
>>> +*.s
>>> +*.ko
>>> +*.so
>>> +*.so.dbg
>>> +*.mod.c
>>> +*.i
>>> +*.lst
>>> +*.symtypes
>>> +*.order
>>> +modules.builtin
>>> +*.elf
>>> +*.bin
>>> +*.gz
>>> +*.bz2
>>> +*.lzma
>>> +*.xz
>>> +*.lzo
>>> +*.patch
>>> +*.gcno
>>
>> I don't think you need to do any of this, just inherit the global one
>> (by not having one here)?
>
> Sorry, that's a holdover from how we used to manage our out-of-tree port and
> can just be deleted.
>
>   https://github.com/riscv/riscv-linux/commit/68032fb592297331a2f2caf246968da7b70373fe
>
>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>>> new file mode 100644
>>> index 000000000000..510ead1d3343
>>> --- /dev/null
>>> +++ b/arch/riscv/Kconfig
>>> +config CPU_RV_GENERIC
>>> +       bool "Generic RISC-V"
>>> +       select CPU_SUPPORTS_32BIT_KERNEL
>>> +       select CPU_SUPPORTS_64BIT_KERNEL
>>
>> Is this even needed at this point? If the only CPU you can pick
>> supports this, you might as well not make it an option (CPU_RV_GENERIC
>> that is), and just make CPU_SUPPORTS_{32,64}BIT_KERNEL 'def_bool y'
>> for now.
>
> I think this is actually broken in the opposite direction: we only support
> 32-bit kernels on RV32 and 64-bit kernels on RV64, not both at the same time.
> I don't really think it makes sense to build a kernel that supports both 32-bit
> and 64-bit on RISC-V (as they're different base ISAs), so I think it'd be
> better to just have a "base ISA" configuration.
>
>   https://github.com/riscv/riscv-linux/commit/695d428d65bf6fe1382d34393e9d07f40b74e1b2
>
> We'll think on this a bit more and get something saner.

Sure, sounds good overall though.

>>> +config SBI_CONSOLE
>>> +       tristate "SBI console support"
>>> +       select TTY
>>> +       default y
>>
>> Usually you end up having a DRIVER_FOO and DRIVER_FOO_CONSOLE option
>> to enable registering it as console.
>>
>> Also, unless there's strong reason to keep it under arch/, it should
>> probably go under drivers/tty/.
>
> In this case "SBI" is the "Supervisor Binary Interface".  This is a set of
> routines that are provided by the platform for OS use that do things like
> writing to the boot console or TLB shootdowns.  The SBI is part of the RISC-V
> ISA, so there isn't a config option for turning it off.  SBI_CONSOLE
> enables/disables the SBI's console support, so I think this option is sane.
>
> It's in arch/riscv because the SBI is part of the RISC-V ISA -- essentially
> there's special SBI instructions that mean "write some register to the console"
> (there's some implementation tricks behind this, so it's really just a
> specification).  That said, I'm fine moving this to drivers.

The same is true for some other drivers. Actually, I wonder if it
might be just as easy to implement a sbi backend for hvc -- see
hvc_udbg.c for an example where, on power, you have a simple get/put
char hypervisor call in a very similar manner.

Either way (keeping discrete sbi driver or implementing hvc backend),
moving to drivers/tty is the right thing here -- we've worked hard on
ARM to get rid of random drivers under arch/ and it'd be nice to not
see new ones intoduced here.


>
>>> +config RVC
>>> +       bool "Use compressed instructions (RV32C or RV64C)"
>>> +       default n
>>
>> What does "use" here mean? Use during build, or allow userspace to use them?
>>
>>> +
>>> +config RV_ATOMIC
>>> +       bool "Use atomic memory instructions (RV32A or RV64A)"
>>> +       default y
>>
>> Same for this.
>
> These mean "tell the compiler that it can emit these instructions when building
> Linux".  Userspace applications can still use these instructions either way.
> How does "Emit compressed instructions when building Linux" sound?
>
>   https://github.com/riscv/riscv-linux/commit/d6e65bd8b7dcfa72578d62e5eb367f680b55f5a8

Sounds good, you can still reference the ISA extensions if you want though.

>>
>>> +config RV_SYSRISCV_ATOMIC
>>> +       bool "Include support for atomic operation syscalls"
>>> +       default n
>>> +       help
>>> +         If atomic memory instructions are present, i.e.,
>>> +         CONFIG_RV_ATOMIC, this includes support for the syscall that
>>> +         provides atomic accesses.  This is only useful to run
>>> +         binaries that require atomic access but were compiled with
>>> +         -mno-atomic.
>>> +
>>> +         If CONFIG_RV_ATOMIC is unset, this option is mandatory.
>>
>> If it's mandatory then Kconfig language should make it so.
>
> I'm not sure what you mean by this.  We have
>
>   config RISCV
>         ...
>         select RV_SYSRISCV_ATOMIC if !RV_ATOMIC
>
> Should this constraint just live within "config RV_SYSRISCV_ATOMIC"?  It seems
> cleaner to have the constraints next to the config definitions.

Ah, I just missed the select.


-Olof

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#1648706 — Re: [patches] Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On Mon, 2017-05-22 at 22:16 -0700, Olof Johansson wrote:
> The same is true for some other drivers. Actually, I wonder if it
> might be just as easy to implement a sbi backend for hvc -- see
> hvc_udbg.c for an example where, on power, you have a simple get/put
> char hypervisor call in a very similar manner.

Rather look at hvc_opal. This is the console driver we use on native
POWER servers with the OPAL firmware, and it calls into a firmware
in a very similar way.

The driver lives in drivers/tty/hvc. It does call some "helpers" in
the arch code that wrap the actual FW calls.

> Either way (keeping discrete sbi driver or implementing hvc backend),
> moving to drivers/tty is the right thing here -- we've worked hard on
> ARM to get rid of random drivers under arch/ and it'd be nice to not
> see new ones intoduced here.

Yup. The reason mostly is that if the tty maintainer needs to do a
subsystem-wide change, he can address all drivers in drivers/tty and
doesn't have to look for others elsewhere in the tree. This is the same
for all subsystems.

Cheers,
Ben.

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#1647640 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

(new top-level subthread here since this is a separate topic):

On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:

> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> new file mode 100644
> index 000000000000..07ef200e0675
> --- /dev/null
> +++ b/arch/riscv/Makefile
> @@ -0,0 +1,64 @@
> +# This file is included by the global makefile so that you can add your own
> +# architecture-specific flags and dependencies. Remember to do have actions
> +# for "archclean" and "archdep" for cleaning up and making dependencies for
> +# this architecture
> +#
> +# This file is subject to the terms and conditions of the GNU General Public
> +# License.  See the file "COPYING" in the main directory of this archive
> +# for more details.
> +#
> +
> +LDFLAGS         :=
> +OBJCOPYFLAGS    := -O binary
> +LDFLAGS_vmlinux :=
> +KBUILD_AFLAGS_MODULE += -fPIC
> +KBUILD_CFLAGS_MODULE += -fPIC
> +
> +ifeq ($(ARCH),riscv)
> +       KBUILD_DEFCONFIG = riscv64_spike
> +else
> +       KBUILD_DEFCONFIG = $(ARCH)_spike
> +endif
> +
> +export BITS
> +ifeq ($(CONFIG_64BIT),y)
> +       BITS := 64
> +       UTS_MACHINE := riscv64
> +
> +       KBUILD_CFLAGS += -mabi=lp64
> +       KBUILD_AFLAGS += -mabi=lp64
> +       KBUILD_MARCH = rv64im
> +       LDFLAGS += -melf64lriscv
> +else
> +       BITS := 32
> +       UTS_MACHINE := riscv32
> +
> +       KBUILD_CFLAGS += -mabi=ilp32
> +       KBUILD_AFLAGS += -mabi=ilp32
> +       KBUILD_MARCH = rv32im
> +       LDFLAGS += -melf32lriscv
> +endif
> +
> +ifeq ($(CONFIG_RV_ATOMIC),y)
> +       KBUILD_RV_ATOMIC = a
> +endif
> +
> +KBUILD_CFLAGS += -Wall
> +
> +ifeq ($(CONFIG_RVC),y)
> +       KBUILD_RVC = c
> +endif
> +
> +KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_RV_ATOMIC)fd$(KBUILD_RVC)
> +
> +KBUILD_CFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_RV_ATOMIC)$(KBUILD_RVC)
> +KBUILD_CFLAGS += -mno-save-restore
> +KBUILD_CFLAGS += -mstrict-align

I built a vanilla gcc-7.1.0 here, with 'riscv64-linux' as target, and I get:

riscv64-linux-gcc: error: unrecognized command line option
'-mstrict-align'; did you mean '-Wstrict-aliasing'?


The suggestion seems completely bogus, but the error is real. Looking
at the gcc sources, I only see strict-align plumbed up on rs6000,
aarch64, m68k(!) and v850. Or am I missing something here?



-Olof

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#1648187 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On Mon, 22 May 2017 22:23:17 PDT (-0700), olof@lixom.net wrote:
> (new top-level subthread here since this is a separate topic):
>
> On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
>> new file mode 100644
>> index 000000000000..07ef200e0675
>> --- /dev/null
>> +++ b/arch/riscv/Makefile
>> @@ -0,0 +1,64 @@
>> +# This file is included by the global makefile so that you can add your own
>> +# architecture-specific flags and dependencies. Remember to do have actions
>> +# for "archclean" and "archdep" for cleaning up and making dependencies for
>> +# this architecture
>> +#
>> +# This file is subject to the terms and conditions of the GNU General Public
>> +# License.  See the file "COPYING" in the main directory of this archive
>> +# for more details.
>> +#
>> +
>> +LDFLAGS         :=
>> +OBJCOPYFLAGS    := -O binary
>> +LDFLAGS_vmlinux :=
>> +KBUILD_AFLAGS_MODULE += -fPIC
>> +KBUILD_CFLAGS_MODULE += -fPIC
>> +
>> +ifeq ($(ARCH),riscv)
>> +       KBUILD_DEFCONFIG = riscv64_spike
>> +else
>> +       KBUILD_DEFCONFIG = $(ARCH)_spike
>> +endif
>> +
>> +export BITS
>> +ifeq ($(CONFIG_64BIT),y)
>> +       BITS := 64
>> +       UTS_MACHINE := riscv64
>> +
>> +       KBUILD_CFLAGS += -mabi=lp64
>> +       KBUILD_AFLAGS += -mabi=lp64
>> +       KBUILD_MARCH = rv64im
>> +       LDFLAGS += -melf64lriscv
>> +else
>> +       BITS := 32
>> +       UTS_MACHINE := riscv32
>> +
>> +       KBUILD_CFLAGS += -mabi=ilp32
>> +       KBUILD_AFLAGS += -mabi=ilp32
>> +       KBUILD_MARCH = rv32im
>> +       LDFLAGS += -melf32lriscv
>> +endif
>> +
>> +ifeq ($(CONFIG_RV_ATOMIC),y)
>> +       KBUILD_RV_ATOMIC = a
>> +endif
>> +
>> +KBUILD_CFLAGS += -Wall
>> +
>> +ifeq ($(CONFIG_RVC),y)
>> +       KBUILD_RVC = c
>> +endif
>> +
>> +KBUILD_AFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_RV_ATOMIC)fd$(KBUILD_RVC)
>> +
>> +KBUILD_CFLAGS += -march=$(KBUILD_MARCH)$(KBUILD_RV_ATOMIC)$(KBUILD_RVC)
>> +KBUILD_CFLAGS += -mno-save-restore
>> +KBUILD_CFLAGS += -mstrict-align
>
> I built a vanilla gcc-7.1.0 here, with 'riscv64-linux' as target, and I get:
>
> riscv64-linux-gcc: error: unrecognized command line option
> '-mstrict-align'; did you mean '-Wstrict-aliasing'?
>
>
> The suggestion seems completely bogus, but the error is real. Looking
> at the gcc sources, I only see strict-align plumbed up on rs6000,
> aarch64, m68k(!) and v850. Or am I missing something here?

We didn't get the "-mstrict-align" patch for RISC-V into the 7.1.0 release.
The boot loader install machine-mode unaligned access handlers, so in theory
you shouldn't need this at all -- it snuck its way in as a debugging attempt
because the Radeon driver was exhibiting some weird behavior.

I'll drop this from the next patch set.

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#1647937 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

Hi Palmer,

On Tue, May 23, 2017 at 2:41 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> --- /dev/null
> +++ b/arch/riscv/Kconfig
> @@ -0,0 +1,300 @@

> +config PLIC
> +       bool "Platform-Level Interrupt Controller"
> +       default y
> +       help
> +          This enables support for the PLIC chip found in standard RISC-V
> +          systems. The PLIC is the top-most interrupt controller found in
> +          the system, connected directly to the core complex. All other
> +          interrupt sources (MSI, GPIO, etc) are subordinate to the PLIC.
> +
> +          If you don't know what to do here, say Y.
> +

I think this symbol belongs in drivers/irqchip/Kconfig, and the corresponding
driver in drivers/irqchip/.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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#1647960 — Re: [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs

On Tue, May 23, 2017 at 2:41 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> ---
>  arch/riscv/.gitignore                |  35 ++++
>  arch/riscv/Kconfig                   | 300 +++++++++++++++++++++++++++++++++++
>  arch/riscv/Makefile                  |  64 ++++++++
>  arch/riscv/configs/riscv32_spike     |  47 ++++++
>  arch/riscv/configs/riscv64_freedom-u |  52 ++++++
>  arch/riscv/configs/riscv64_qemu      |  64 ++++++++
>  arch/riscv/configs/riscv64_spike     |  45 ++++++
>  7 files changed, 607 insertions(+)
>  create mode 100644 arch/riscv/.gitignore
>  create mode 100644 arch/riscv/Kconfig
>  create mode 100644 arch/riscv/Makefile
>  create mode 100644 arch/riscv/configs/riscv32_spike
>  create mode 100644 arch/riscv/configs/riscv64_freedom-u
>  create mode 100644 arch/riscv/configs/riscv64_qemu
>  create mode 100644 arch/riscv/configs/riscv64_spike
>
> diff --git a/arch/riscv/.gitignore b/arch/riscv/.gitignore
> new file mode 100644
> index 000000000000..376d06eb5d52
> --- /dev/null
> +++ b/arch/riscv/.gitignore
> @@ -0,0 +1,35 @@
> +# Now un-ignore all files.
> +!*
> +
> +# But then re-ignore the files listed in the Linux .gitignore
> +# Normal rules
> +#
> +.*
> +*.o
> +*.o.*
> +*.a

This doesn't seem to belong here: There is no reason for riscv
to be different from all other architectures. Is something wrong
with the top-level .gitignore? If so, we should just fix it there.

> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> new file mode 100644
> index 000000000000..510ead1d3343
> --- /dev/null
> +++ b/arch/riscv/Kconfig
> @@ -0,0 +1,300 @@
> +#
> +# For a description of the syntax of this configuration file,
> +# see Documentation/kbuild/kconfig-language.txt.
> +#
> +
> +config RISCV
> +       def_bool y
> +       select OF
> +       select OF_EARLY_FLATTREE
> +       select OF_IRQ
> +       select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
> +       select ARCH_WANT_FRAME_POINTERS
> +       select CLONE_BACKWARDS
> +       select COMMON_CLK
> +       select GENERIC_CLOCKEVENTS
> +       select GENERIC_CPU_DEVICES
> +       select GENERIC_IRQ_SHOW
> +       select GENERIC_PCI_IOMAP

You normally don't want GENERIC_PCI_IOMAP, unless your
inb()/outb() uses other instructions than your readl()/writel()

> +config MMU
> +       def_bool y

Just a general question: has there been any interest in a no-MMU
version?

> +# even on 32-bit, physical (and DMA) addresses are > 32-bits
> +config ARCH_PHYS_ADDR_T_64BIT
> +       def_bool y
> +
> +config ARCH_DMA_ADDR_T_64BIT
> +       def_bool y

Are you required to use 64-bit addressing for RAM on 32-bit
architectures though? Using 32-bit dma_addr_t and phys_addr_t
when possible makes some code noticeably more efficient.

> +config PGTABLE_LEVELS
> +       int
> +       default 3 if 64BIT
> +       default 2

With 2-level page tables, you usually can't address much more
than 32-bit physical memory anyway, so I'd guess that most
32-bit chips would actually put their RAM under the 4GB boundary.

> +config RV_ATOMIC
> +       bool "Use atomic memory instructions (RV32A or RV64A)"
> +       default y
> +
> +config RV_SYSRISCV_ATOMIC
> +       bool "Include support for atomic operation syscalls"
> +       default n
> +       help
> +         If atomic memory instructions are present, i.e.,
> +         CONFIG_RV_ATOMIC, this includes support for the syscall that
> +         provides atomic accesses.  This is only useful to run
> +         binaries that require atomic access but were compiled with
> +         -mno-atomic.
> +
> +         If CONFIG_RV_ATOMIC is unset, this option is mandatory.

Just express this in Kconfig terms to prevent misconfiguration:

config RV_SYSRISCV_ATOMIC
       bool "Include support for atomic operation syscalls" if RV_ATOMIC
       default !RV_ATOMIC

I wonder what the cost would be of always providing the syscalls
for compatibility. This is also something worth putting into a VDSO
instead of exposing the syscall:

That way, user space that is built with -mno-atomic can call into
the vdso, which depending on the hardware support will perform
the atomic operation directly or enter the syscall.

> +config PCI_DOMAINS
> +       def_bool PCI
> +
> +config PCI_DOMAINS_GENERIC
> +       def_bool PCI
> +
> +config PCI_SYSCALL
> +       def_bool PCI

I don't think you want PCI_SYSCALL

        Arnd

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#1647531 — [PATCH 3/7] RISC-V: Device Tree Documentation

---
 .../interrupt-controller/riscv,cpu-intc.txt        | 46 ++++++++++++++++++++++
 .../bindings/interrupt-controller/riscv,plic0.txt  | 44 +++++++++++++++++++++
 2 files changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
new file mode 100644
index 000000000000..62f02e834ff9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
@@ -0,0 +1,46 @@
+RISC-V Hart-Level Interrupt Controller (HLIC)
+---------------------------------------------
+
+RISC-V cores include Control Status Registers (CSRs) which are local to each
+hart and can be read or written by software. Some of these CSRs are used to
+control local interrupts connected to the core.
+
+Typical examples of local interrupts on a RISC-V core include: software IPI
+interrupts, timer interrupts, and a link to the PLIC interrupt controller.
+
+Required properties:
+- compatible : "riscv,cpu-intc"
+- #interrupt-cells : should be <1>
+- interrupt-controller : Identifies the node as an interrupt controller
+
+Furthermore, this interrupt-controller MUST be embedded inside the cpu
+definition of the hart whose CSRs control these local interrupts.
+
+Example:
+
+	cpu1: cpu@1 {
+		clock-frequency = <1600000000>;
+		compatible = "riscv";
+		d-cache-block-size = <64>;
+		d-cache-sets = <64>;
+		d-cache-size = <16384>;
+		d-tlb-sets = <1>;
+		d-tlb-size = <32>;
+		device_type = "cpu";
+		i-cache-block-size = <64>;
+		i-cache-sets = <64>;
+		i-cache-size = <16384>;
+		i-tlb-sets = <1>;
+		i-tlb-size = <32>;
+		mmu-type = "riscv,sv39";
+		next-level-cache = <&L2>;
+		reg = <1>;
+		riscv,isa = "rv64imac";
+		status = "okay";
+		tlb-split;
+		cpu1-intc: interrupt-controller {
+			#interrupt-cells = <1>;
+			compatible = "riscv,cpu-intc";
+			interrupt-controller;
+		};
+	};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt b/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt
new file mode 100644
index 000000000000..c05b5806f7d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,plic0.txt
@@ -0,0 +1,44 @@
+RISC-V Platform-Level Interrupt Controller (PLIC)
+-------------------------------------------------
+
+RISC-V cores typically include a PLIC, which route interrupts from multiple
+devices to multiple hart contexts.  The PLIC is connected to the interrupt
+controller embedded in a RISC-V core via the interrupt-related CSRs.
+
+A hart context is a priviledge mode in a hardware execution thread.  For
+example, in an 4 core system with 2-way SMT, you have 8 harts and probably
+at least two priviledge modes per hart; machine mode and supervisor mode.
+
+Each interrupt can be enabled on per-context basis. Any context can claim
+a pending enabled interrupt and then release it once it has been handled.
+
+Each interrupt has a configurable priority. Higher priority interrupts are
+serviced firs. Each context can specify a priority threshold. Interrupts
+with priority below this threshold will not cause the PLIC to raise its
+interrupt line leading to the context.
+
+Required properties:
+- compatible : "riscv,plic0"
+- #address-cells : should be <0>
+- #interrupt-cells : should be <1>
+- interrupt-controller : Identifies the node as an interrupt controller
+- reg : Should contain 1 register range (address and length)
+- riscv,ndev : Specifies the number of interrupts attached to the PLIC
+- interrupts-extended : Specifies which contexts are connected to the PLIC
+
+Example:
+
+	plic: interrupt-controller@c000000 {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		compatible = "riscv,plic0";
+		interrupt-controller;
+		interrupts-extended = <
+			&cpu0-intc 11
+			&cpu1-intc 11 &cpu1-intc 9
+			&cpu2-intc 11 &cpu2-intc 9
+			&cpu3-intc 11 &cpu3-intc 9
+			&cpu4-intc 11 &cpu4-intc 9>;
+		reg = <0xc000000 0x4000000>;
+		riscv,ndev = <10>;
+	};
-- 
2.13.0

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#1647969 — Re: [PATCH 3/7] RISC-V: Device Tree Documentation

On Tue, May 23, 2017 at 2:41 AM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> ---
>  .../interrupt-controller/riscv,cpu-intc.txt        | 46 ++++++++++++++++++++++
>  .../bindings/interrupt-controller/riscv,plic0.txt  | 44 +++++++++++++++++++++

The patch needs a description, and should be sent to the irqchip maintainers
and the devicetree maintainers for review, along for the respective
drivers/irqchip/
patch.

       Arnd

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#1647549

Hi Palmer,

On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> We'd like to submit for inclusion in Linux a port for the RISC-V architecture.
> While it is doubtlessly not complete, we think it is far enough along to start
> the upstreaming process.  Our binutils and GCC ports have been accepted and
> released, and we plan on submitting glibc patches soon.
>
> This port targets Version 1.10 of the RISC-V Privileged ISA, and supports both
> the RV32 and RV64 user ISAs.  The RISC-V community and the 60-some member
> companies of the RISC-V Foundation are quite eager to have a single, standard
> Linux port.  We thank you in advance for your help in this process and for your
> feedback on the software contribution itself.
>
> These patches build and boot on top of 4.12-rc2.  I understand that the merge
> window is closed, but it was suggested that the best time to submit a new
> architecture port would be right after an RC2 as the earliest point at which
> the tree is usually generally churn-free enough.  While we optimistically hope
> that we can get the port in for the 4.13 merge window, we're also eager to
> ensure that the user-visible ABI is sane so we can proceed with our glibc port.
> We'd like to at least get any user ABI issues shaken out as soon as possible,
> even if we don't make it into 4.13.

Time is right for review and eventual merge of this. Whether it makes
4.13 depends on how much discussion ensues. :)

> Albert and I will volunteer to maintain this port if it's OK with everyone.

It always makes sense to have architecture-knowledge people maintain
it; no complaints from me.

What we've seen been useful on other platforms (i.e. arm/arm64) is to
offload the per-vendor stuff to a separate tree. It might or might not
be needed here; likely to start out it won't be enough material to
need it.

> We'd like to thank the various members of the RISC-V software community who
> have helped us with the port.
>
> Thanks!
>
> In addition to the threaded messages, our port can be found on Git Hib
>
>   https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v1
>
> [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64}
> [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs
> [PATCH 3/7] RISC-V: Device Tree Documentation
> [PATCH 4/7] RISC-V: arch/riscv/include
> [PATCH 5/7] RISC-V: arch/riscv/lib
> [PATCH 6/7] RISC-V: arch/riscv/kernel
> [PATCH 7/7] RISC-V: arch/riscv/mm

So, one overall comment on this patchset is that it's not bisectable
(i.e. early patches add Makefile contents that refers to directories
not yet introduced).

While it's not overly important to really split up a new architecture
introduction into small incremental patches, we generally strive to
have the tree fully buildable at any given commit. Some minor
rearranging would alleviate these problems.

Also, none of the patches seem to have any descriptions. Adding some
high-level descriptions of what's in each patch in the patch itself is
useful both for reviewing now, and for educating anyone coming along
later on trying to learn about the code and why it's been implemented
as it has.

I'll add more comments on some of the individual patches; expect this
review to take a little while. Reposting once or twice a week to show
incorporated changes can be useful; more than that and it can be
harder to follow along in the discussion. It all depends on how much
comments you end up receiving.


-Olof

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#1647554

On 05/22/17 18:16, Olof Johansson wrote:
> Hi Palmer,
> 
> On Mon, May 22, 2017 at 5:41 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> 
>> In addition to the threaded messages, our port can be found on Git Hib
>>
>>   https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v1
>>
>> [PATCH 1/7] RISC-V: Top-Level Makefile for riscv{32,64}
>> [PATCH 2/7] RISC-V: arch/riscv Makefile and Kconfigs
>> [PATCH 3/7] RISC-V: Device Tree Documentation
>> [PATCH 4/7] RISC-V: arch/riscv/include
>> [PATCH 5/7] RISC-V: arch/riscv/lib
>> [PATCH 6/7] RISC-V: arch/riscv/kernel
>> [PATCH 7/7] RISC-V: arch/riscv/mm
> 
> So, one overall comment on this patchset is that it's not bisectable
> (i.e. early patches add Makefile contents that refers to directories
> not yet introduced).
> 
> While it's not overly important to really split up a new architecture
> introduction into small incremental patches, we generally strive to
> have the tree fully buildable at any given commit. Some minor
> rearranging would alleviate these problems.

Neither the email patches nor the git tree have any Signed-off-by:
entries AFAICT.

-- 
~Randy

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