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[PATCH v2 0/5] Add support for the STM32F4 CRC32

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  [PATCH v2 0/5] Add support for the STM32F4 CRC32 Cosar Dindar <cosardindar@gmail.com> - 2017-05-20 15:40 +0200
    [PATCH v2 5/5] ARM: dts: stm32: Add CRC support to stm32f429 Cosar Dindar <cosardindar@gmail.com> - 2017-05-20 15:40 +0200
    [PATCH v2 1/5] crypto : stm32 - Add STM32F4 CRC32 support Cosar Dindar <cosardindar@gmail.com> - 2017-05-20 15:40 +0200
    [PATCH v2 3/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board Cosar Dindar <cosardindar@gmail.com> - 2017-05-20 15:40 +0200
      Re: [PATCH v2 3/5] ARM: dts: stm32: enable CRC32 on stm32429-disco  board kbuild test robot <lkp@intel.com> - 2017-05-22 13:20 +0200

#1646124 — [PATCH v2 0/5] Add support for the STM32F4 CRC32

This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.

Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0xFFFFFFFF.

Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0xFFFFFFFF.

Cosar Dindar (5):
  crypto : stm32 - Add STM32F4 CRC32 support
  dt-bindings : Document the STM32F4 CRC32 binding
  ARM: dts: stm32: enable CRC32 on stm32429-disco board
  ARM: dts: stm32: enable CRC32 on stm32429i-eval board
  ARM: dts: stm32: Add CRC support to stm32f429

 .../devicetree/bindings/crypto/st,stm32-crc.txt    |  4 +-
 arch/arm/boot/dts/stm32429i-eval.dts               |  4 ++
 arch/arm/boot/dts/stm32f429-disco.dts              |  4 ++
 arch/arm/boot/dts/stm32f429.dtsi                   |  7 +++
 drivers/crypto/stm32/stm32_crc32.c                 | 68 ++++++++++++++++++----
 5 files changed, 75 insertions(+), 12 deletions(-)

-- 
2.7.4

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#1646126 — [PATCH v2 5/5] ARM: dts: stm32: Add CRC support to stm32f429

Add CRC32 Crypto support to stm32f429.

Signed-off-by: Cosar Dindar <cosardindar@gmail.com>
---
 arch/arm/boot/dts/stm32f429.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index b2a2b5c..18343de 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -766,6 +766,13 @@
 			};
 		};
 
+		crc: crc@40023000 {
+			compatible = "st,stm32f4-crc";
+			reg = <0x40023000 0x400>;
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
+			status = "disabled";
+		};
+
 		rcc: rcc@40023810 {
 			#reset-cells = <1>;
 			#clock-cells = <2>;
-- 
2.7.4

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#1646127 — [PATCH v2 1/5] crypto : stm32 - Add STM32F4 CRC32 support

This patch adds CRC (CRC32 Crypto) support for STM32F4 series.

As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0xFFFFFFFF (key).
CRC32C Castagnoli algorithm is not used.

Signed-off-by: Cosar Dindar <cosardindar@gmail.com>
---
 drivers/crypto/stm32/stm32_crc32.c | 68 ++++++++++++++++++++++++++++++++------
 1 file changed, 58 insertions(+), 10 deletions(-)

diff --git a/drivers/crypto/stm32/stm32_crc32.c b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
 #include <linux/bitrev.h>
 #include <linux/clk.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 
 #include <crypto/internal/hash.h>
@@ -39,6 +40,9 @@ struct stm32_crc {
 	struct clk       *clk;
 	u8               pending_data[sizeof(u32)];
 	size_t           nb_pending_bytes;
+	bool             key_support;
+	bool             poly_support;
+	bool             reverse_support;
 };
 
 struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
 	}
 	spin_unlock_bh(&crc_list.lock);
 
-	/* Reset, set key, poly and configure in bit reverse mode */
-	writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
-	writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
-	writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+	/* set key */
+	if (ctx->crc->key_support) {
+		writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+	} else if (mctx->key != CRC_INIT_DEFAULT) {
+		dev_err(ctx->crc->dev, "Unsupported key value! Should be: 0x%x\n",
+			CRC_INIT_DEFAULT);
+		return -EINVAL;
+	}
+
+	/* set poly */
+	if (ctx->crc->poly_support)
+		writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+	/* reset and configure in bit reverse mode if supported */
+	if (ctx->crc->reverse_support)
+		writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+	else
+		writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+	/* store partial result */
+	if (!ctx->crc->reverse_support)
+		ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+	else
+		ctx->partial = readl(ctx->crc->regs + CRC_DR);
 
-	/* Store partial result */
-	ctx->partial = readl(ctx->crc->regs + CRC_DR);
 	ctx->crc->nb_pending_bytes = 0;
 
 	return 0;
@@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
 
 		if (crc->nb_pending_bytes == sizeof(u32)) {
 			/* Process completed pending data */
-			writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+			if (!ctx->crc->reverse_support)
+				writel(bitrev32(*(u32 *)crc->pending_data),
+				       crc->regs + CRC_DR);
+			else
+				writel(*(u32 *)crc->pending_data,
+				       crc->regs + CRC_DR);
 			crc->nb_pending_bytes = 0;
 		}
 	}
@@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
 	d32 = (u32 *)d8;
 	for (i = 0; i < length >> 2; i++)
 		/* Process 32 bits data */
-		writel(*(d32++), crc->regs + CRC_DR);
+		if (!ctx->crc->reverse_support)
+			writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+		else
+			writel(*(d32++), crc->regs + CRC_DR);
 
 	/* Store partial result */
-	ctx->partial = readl(crc->regs + CRC_DR);
+	if (!ctx->crc->reverse_support)
+		ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+	else
+		ctx->partial = readl(crc->regs + CRC_DR);
 
 	/* Check for pending data (non 32 bits) */
 	length &= 3;
@@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
 	struct stm32_crc *crc;
 	struct resource *res;
 	int ret;
+	int algs_size;
 
 	crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
 	if (!crc)
@@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	/* set key, poly and reverse support if device is of F7 series */
+	if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
+		crc->key_support = true;
+		crc->poly_support = true;
+		crc->reverse_support = true;
+	}
+
 	platform_set_drvdata(pdev, crc);
 
 	spin_lock(&crc_list.lock);
 	list_add(&crc->list, &crc_list.dev_list);
 	spin_unlock(&crc_list.lock);
 
-	ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
+	/* For F4 series only CRC32 algorithm will be used */
+	if (of_device_is_compatible(crc->dev->of_node, "st,stm32f4-crc"))
+		algs_size = 1;
+	else
+		algs_size = ARRAY_SIZE(algs);
+
+	ret = crypto_register_shashes(algs, algs_size);
 	if (ret) {
 		dev_err(dev, "Failed to register\n");
 		clk_disable_unprepare(crc->clk);
@@ -304,6 +351,7 @@ static int stm32_crc_remove(struct platform_device *pdev)
 
 static const struct of_device_id stm32_dt_ids[] = {
 	{ .compatible = "st,stm32f7-crc", },
+	{ .compatible = "st,stm32f4-crc", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
-- 
2.7.4

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#1646128 — [PATCH v2 3/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board

Enable the CRC32 crypto on stm32429-disco board.

Signed-off-by: Cosar Dindar <cosardindar@gmail.com>
---
 arch/arm/boot/dts/stm32f429-disco.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 191fa50..ae47cde 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -102,6 +102,10 @@
 	clock-frequency = <8000000>;
 };
 
+&crc {
+	status = "okay";
+};
+
 &rtc {
 	assigned-clocks = <&rcc 1 CLK_RTC>;
 	assigned-clock-parents = <&rcc 1 CLK_LSI>;
-- 
2.7.4

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#1646758 — Re: [PATCH v2 3/5] ARM: dts: stm32: enable CRC32 on stm32429-disco board

[Multipart message — attachments visible in raw view] — view raw

Hi Cosar,

[auto build test ERROR on cryptodev/master]
[also build test ERROR on v4.12-rc2 next-20170522]
[cannot apply to robh/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Cosar-Dindar/Add-support-for-the-STM32F4-CRC32/20170522-151254
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

Note: the linux-review/Cosar-Dindar/Add-support-for-the-STM32F4-CRC32/20170522-151254 HEAD 6822bdfe94793c70fe6812817f26f02db23e2593 builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/stm32f429-disco.dts:105.1-5 Label or path crc not found
   FATAL ERROR: Syntax error parsing input tree

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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