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| Started by | Rob Herring <robh@kernel.org> |
|---|---|
| First post | 2017-05-16 02:20 +0200 |
| Last post | 2017-05-18 15:50 +0200 |
| Articles | 2 — 2 participants |
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Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Rob Herring <robh@kernel.org> - 2017-05-16 02:20 +0200
Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 Geetha Akula <geethasowjanya.akula@gmail.com> - 2017-05-18 15:50 +0200
| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2017-05-16 02:20 +0200 |
| Subject | Re: [v6 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74 |
| Message-ID | <tHynv-6J0-7@gated-at.bofh.it> |
DT changes should go to DT list. On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya <gakula@caviumnetworks.com> wrote: > From: Linu Cherian <linu.cherian@cavium.com> > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > This option when turned on, replaces all page 1 offsets used for > EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. > > SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY, > since resource size can be either 64k/128k. > For this, arm_smmu_device_dt_probe/acpi_probe has been moved before > platform_get_resource call, so that SMMU options are set beforehand. > > Signed-off-by: Linu Cherian <linu.cherian@cavium.com> > Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > --- > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ > drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++----- > 3 files changed, 56 insertions(+), 15 deletions(-) > > diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt > index 10f2ddd..4693a32 100644 > --- a/Documentation/arm64/silicon-errata.txt > +++ b/Documentation/arm64/silicon-errata.txt > @@ -62,6 +62,7 @@ stable kernels. > | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | > | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | > | Cavium | ThunderX SMMUv2 | #27704 | N/A | > +| Cavium | ThunderX2 SMMUv3| #74 | N/A | > | | | | | > | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | > | | | | | > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > index be57550..e6da62b 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt > @@ -49,6 +49,12 @@ the PCIe specification. > - hisilicon,broken-prefetch-cmd > : Avoid sending CMD_PREFETCH_* commands to the SMMU. > > +- cavium-cn99xx,broken-page1-regspace "cavium-cn99xx" is not a vendor. I'm sure you have an SoC specific compatible string, so use that to enable any errata work-arounds. Rob
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| From | Geetha Akula <geethasowjanya.akula@gmail.com> |
|---|---|
| Date | 2017-05-18 15:50 +0200 |
| Message-ID | <tItYu-3le-13@gated-at.bofh.it> |
| In reply to | #1642140 |
On Tue, May 16, 2017 at 5:45 AM, Rob Herring <robh@kernel.org> wrote: > DT changes should go to DT list. > > On Fri, May 12, 2017 at 7:41 AM, Geetha sowjanya > <gakula@caviumnetworks.com> wrote: >> From: Linu Cherian <linu.cherian@cavium.com> >> >> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space >> and PAGE0_REGS_ONLY option is enabled as an errata workaround. >> This option when turned on, replaces all page 1 offsets used for >> EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. >> >> SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY, >> since resource size can be either 64k/128k. >> For this, arm_smmu_device_dt_probe/acpi_probe has been moved before >> platform_get_resource call, so that SMMU options are set beforehand. >> >> Signed-off-by: Linu Cherian <linu.cherian@cavium.com> >> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com> >> --- >> Documentation/arm64/silicon-errata.txt | 1 + >> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ >> drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++----- >> 3 files changed, 56 insertions(+), 15 deletions(-) >> >> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt >> index 10f2ddd..4693a32 100644 >> --- a/Documentation/arm64/silicon-errata.txt >> +++ b/Documentation/arm64/silicon-errata.txt >> @@ -62,6 +62,7 @@ stable kernels. >> | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | >> | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | >> | Cavium | ThunderX SMMUv2 | #27704 | N/A | >> +| Cavium | ThunderX2 SMMUv3| #74 | N/A | >> | | | | | >> | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | >> | | | | | >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt >> index be57550..e6da62b 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt >> @@ -49,6 +49,12 @@ the PCIe specification. >> - hisilicon,broken-prefetch-cmd >> : Avoid sending CMD_PREFETCH_* commands to the SMMU. >> >> +- cavium-cn99xx,broken-page1-regspace > > "cavium-cn99xx" is not a vendor. > > I'm sure you have an SoC specific compatible string, so use that to > enable any errata work-arounds. > > Rob Hi Rob, The "cavium-cn99xx" indeed vendor specific. "cavium" is the vendor and "cn99xx" is the chip model number. We can't use just the vendor name because, in future their might be other model chips from the same vendor. Thank you, Geetha.
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