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| Started by | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| First post | 2017-05-19 02:20 +0200 |
| Last post | 2017-05-19 20:20 +0200 |
| Articles | 2 — 2 participants |
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Re: [PATCH v2] drm/pl111: Register the clock divider and use it. Stephen Boyd <sboyd@codeaurora.org> - 2017-05-19 02:20 +0200
Re: [PATCH v2] drm/pl111: Register the clock divider and use it. Eric Anholt <eric@anholt.net> - 2017-05-19 20:20 +0200
| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2017-05-19 02:20 +0200 |
| Subject | Re: [PATCH v2] drm/pl111: Register the clock divider and use it. |
| Message-ID | <tIDOa-2mO-1@gated-at.bofh.it> |
On 05/08, Eric Anholt wrote:
> This is required for the panel to work on bcm911360, where CLCDCLK is
> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the
> CLCDCLK, for platforms that have a settable rate on that one.
>
> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
> COMMON_CLK.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
One minor comment below
> diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
> index 39a5c33bce7d..2d924a6bf43c 100644
> --- a/drivers/gpu/drm/pl111/pl111_display.c
> +++ b/drivers/gpu/drm/pl111/pl111_display.c
> @@ -288,6 +296,126 @@ const struct drm_simple_display_pipe_funcs pl111_display_funcs = {
[...]
> +
> + return 0;
> +}
> +
> +const struct clk_ops pl111_clk_div_ops = {
static?
> + .recalc_rate = pl111_clk_div_recalc_rate,
> + .round_rate = pl111_clk_div_round_rate,
> + .set_rate = pl111_clk_div_set_rate,
> +};
> +
> +static int
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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| From | Eric Anholt <eric@anholt.net> |
|---|---|
| Date | 2017-05-19 20:20 +0200 |
| Message-ID | <tIUFj-5T5-7@gated-at.bofh.it> |
| In reply to | #1644963 |
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Stephen Boyd <sboyd@codeaurora.org> writes:
> On 05/08, Eric Anholt wrote:
>> This is required for the panel to work on bcm911360, where CLCDCLK is
>> the fixed 200Mhz AXI41 clock. The rate set is still passed up to the
>> CLCDCLK, for platforms that have a settable rate on that one.
>>
>> v2: Set SET_RATE_PARENT (caught by Linus Walleij), depend on
>> COMMON_CLK.
>>
>> Signed-off-by: Eric Anholt <eric@anholt.net>
>
> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
>
> One minor comment below
>
>> diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
>> index 39a5c33bce7d..2d924a6bf43c 100644
>> --- a/drivers/gpu/drm/pl111/pl111_display.c
>> +++ b/drivers/gpu/drm/pl111/pl111_display.c
>> @@ -288,6 +296,126 @@ const struct drm_simple_display_pipe_funcs pl111_display_funcs = {
> [...]
>> +
>> + return 0;
>> +}
>> +
>> +const struct clk_ops pl111_clk_div_ops = {
>
> static?
Fixed, thanks.
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