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[PATCH 1/8 v2] clocksource/drivers/fttmr010: Fix the clock handling

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  [PATCH 1/8 v2] clocksource/drivers/fttmr010: Fix the clock handling Linus Walleij <linus.walleij@linaro.org> - 2017-05-18 22:20 +0200
    [PATCH 6/8 v2] clocksource/drivers/fttmr010: Switch to use TIMER2 src Linus Walleij <linus.walleij@linaro.org> - 2017-05-18 22:20 +0200
    [PATCH 2/8 v2] clocksource/drivers/fttmr010: Merge FTTMR010 DT bindings Linus Walleij <linus.walleij@linaro.org> - 2017-05-18 22:20 +0200
      Re: [PATCH 2/8 v2] clocksource/drivers/fttmr010: Merge FTTMR010 DT bindings Joel Stanley <joel@jms.id.au> - 2017-05-19 07:20 +0200
    [PATCH 3/8 v2] clocksource/drivers/fttmr010: Drop Gemini specifics Linus Walleij <linus.walleij@linaro.org> - 2017-05-18 22:20 +0200

#1644893 — [PATCH 1/8 v2] clocksource/drivers/fttmr010: Fix the clock handling

We need to also prepare and enable the clock we are using to get
the right reference count and avoid it being shut off.

Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Added Jonas' Tested-by, no functional changes.
---
 drivers/clocksource/timer-fttmr010.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c
index b4a6f1e4bc54..58ce017e4a65 100644
--- a/drivers/clocksource/timer-fttmr010.c
+++ b/drivers/clocksource/timer-fttmr010.c
@@ -238,12 +238,18 @@ static int __init fttmr010_timer_of_init(struct device_node *np)
 	 * and using EXTCLK is not supported in the driver.
 	 */
 	struct clk *clk;
+	int ret;
 
 	clk = of_clk_get_by_name(np, "PCLK");
 	if (IS_ERR(clk)) {
-		pr_err("could not get PCLK");
+		pr_err("could not get PCLK\n");
 		return PTR_ERR(clk);
 	}
+	ret = clk_prepare_enable(clk);
+	if (ret) {
+		pr_err("failed to enable PCLK\n");
+		return ret;
+	}
 	tick_rate = clk_get_rate(clk);
 
 	return fttmr010_timer_common_init(np);
-- 
2.9.3

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#1644896 — [PATCH 6/8 v2] clocksource/drivers/fttmr010: Switch to use TIMER2 src

This switches the clocksource to TIMER2 like the Moxart driver
does. Mainly to make it more similar to the Moxart/Aspeed driver
but also because it seems more neat to use the timers in order:
use timer 1, then timer 2.

Cc: Joel Stanley <joel@jms.id.au>
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Added Jonas' Tested-by, no functional changes.
---
 drivers/clocksource/timer-fttmr010.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c
index 9df14cf13808..2d915d1455ab 100644
--- a/drivers/clocksource/timer-fttmr010.c
+++ b/drivers/clocksource/timer-fttmr010.c
@@ -49,9 +49,6 @@
 #define TIMER_1_CR_UPDOWN	BIT(9)
 #define TIMER_2_CR_UPDOWN	BIT(10)
 #define TIMER_3_CR_UPDOWN	BIT(11)
-#define TIMER_DEFAULT_FLAGS	(TIMER_1_CR_UPDOWN | \
-				 TIMER_3_CR_ENABLE | \
-				 TIMER_3_CR_UPDOWN)
 
 #define TIMER_1_INT_MATCH1	BIT(0)
 #define TIMER_1_INT_MATCH2	BIT(1)
@@ -80,7 +77,7 @@ static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
 
 static u64 notrace fttmr010_read_sched_clock(void)
 {
-	return readl(local_fttmr->base + TIMER3_COUNT);
+	return readl(local_fttmr->base + TIMER2_COUNT);
 }
 
 static int fttmr010_timer_set_next_event(unsigned long cycles,
@@ -230,19 +227,21 @@ static int __init fttmr010_timer_init(struct device_node *np)
 	 */
 	writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
 	writel(0, fttmr010->base + TIMER_INTR_STATE);
-	writel(TIMER_DEFAULT_FLAGS, fttmr010->base + TIMER_CR);
+	/* Enable timer 1 count up, timer 2 count up */
+	writel((TIMER_1_CR_UPDOWN | TIMER_2_CR_ENABLE | TIMER_2_CR_UPDOWN),
+	       fttmr010->base + TIMER_CR);
 
 	/*
 	 * Setup free-running clocksource timer (interrupts
 	 * disabled.)
 	 */
 	local_fttmr = fttmr010;
-	writel(0, fttmr010->base + TIMER3_COUNT);
-	writel(0, fttmr010->base + TIMER3_LOAD);
-	writel(0, fttmr010->base + TIMER3_MATCH1);
-	writel(0, fttmr010->base + TIMER3_MATCH2);
-	clocksource_mmio_init(fttmr010->base + TIMER3_COUNT,
-			      "FTTMR010-TIMER3",
+	writel(0, fttmr010->base + TIMER2_COUNT);
+	writel(0, fttmr010->base + TIMER2_LOAD);
+	writel(0, fttmr010->base + TIMER2_MATCH1);
+	writel(0, fttmr010->base + TIMER2_MATCH2);
+	clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
+			      "FTTMR010-TIMER2",
 			      fttmr010->tick_rate,
 			      300, 32, clocksource_mmio_readl_up);
 	sched_clock_register(fttmr010_read_sched_clock, 32,
-- 
2.9.3

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#1644899 — [PATCH 2/8 v2] clocksource/drivers/fttmr010: Merge FTTMR010 DT bindings

This merges the Moxa and FTTMR010 device tree bindings into the
Faraday binding document to avoid confusion.

The FTTMR010 is the IP block used by these SoCs, in vanilla
or modified variant.

The Aspeed variant is modified such that it is no longer fully
register-compatible with FTTMR010 so for this reason it is not
listed with two compatible strings, instead just one.

Cc: Joel Stanley <joel@jms.id.au>
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Added Jonas' Tested-by, no functional changes.
---
 .../devicetree/bindings/timer/faraday,fttmr010.txt    |  4 +++-
 .../devicetree/bindings/timer/moxa,moxart-timer.txt   | 19 -------------------
 2 files changed, 3 insertions(+), 20 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
index b73ca6cd07f8..6e18bd662ccb 100644
--- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
+++ b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
@@ -7,7 +7,9 @@ Required properties:
 
 - compatible : Must be one of
   "faraday,fttmr010"
-  "cortina,gemini-timer"
+  "cortina,gemini-timer", "faraday,fttmr010"
+  "moxa,moxart-timer", "faraday,fttmr010"
+  "aspeed,ast2400-timer"
 - reg : Should contain registers location and length
 - interrupts : Should contain the three timer interrupts usually with
   flags for falling edge
diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
deleted file mode 100644
index e207c11630af..000000000000
--- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-MOXA ART timer
-
-Required properties:
-
-- compatible : Must be one of:
- 	- "moxa,moxart-timer"
- 	- "aspeed,ast2400-timer"
-- reg : Should contain registers location and length
-- interrupts : Should contain the timer interrupt number
-- clocks : Should contain phandle for the clock that drives the counter
-
-Example:
-
-	timer: timer@98400000 {
-		compatible = "moxa,moxart-timer";
-		reg = <0x98400000 0x42>;
-		interrupts = <19 1>;
-		clocks = <&coreclk>;
-	};
-- 
2.9.3

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#1645206 — Re: [PATCH 2/8 v2] clocksource/drivers/fttmr010: Merge FTTMR010 DT bindings

On Fri, May 19, 2017 at 4:16 AM, Linus Walleij <linus.walleij@linaro.org> wrote:
> This merges the Moxa and FTTMR010 device tree bindings into the
> Faraday binding document to avoid confusion.
>
> The FTTMR010 is the IP block used by these SoCs, in vanilla
> or modified variant.
>
> The Aspeed variant is modified such that it is no longer fully
> register-compatible with FTTMR010 so for this reason it is not
> listed with two compatible strings, instead just one.
>
> Cc: Joel Stanley <joel@jms.id.au>
> Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Acked-by: Joel Stanley <joel@jms.id.au>

> ---
> ChangeLog v1->v2:
> - Added Jonas' Tested-by, no functional changes.
> ---
>  .../devicetree/bindings/timer/faraday,fttmr010.txt    |  4 +++-
>  .../devicetree/bindings/timer/moxa,moxart-timer.txt   | 19 -------------------
>  2 files changed, 3 insertions(+), 20 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
> index b73ca6cd07f8..6e18bd662ccb 100644
> --- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
> +++ b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
> @@ -7,7 +7,9 @@ Required properties:
>
>  - compatible : Must be one of
>    "faraday,fttmr010"
> -  "cortina,gemini-timer"
> +  "cortina,gemini-timer", "faraday,fttmr010"
> +  "moxa,moxart-timer", "faraday,fttmr010"
> +  "aspeed,ast2400-timer"

The same bindings apply for the ast2500.

Cheers,

Joel


>  - reg : Should contain registers location and length
>  - interrupts : Should contain the three timer interrupts usually with
>    flags for falling edge
> diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
> deleted file mode 100644
> index e207c11630af..000000000000
> --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -MOXA ART timer
> -
> -Required properties:
> -
> -- compatible : Must be one of:
> -       - "moxa,moxart-timer"
> -       - "aspeed,ast2400-timer"
> -- reg : Should contain registers location and length
> -- interrupts : Should contain the timer interrupt number
> -- clocks : Should contain phandle for the clock that drives the counter
> -
> -Example:
> -
> -       timer: timer@98400000 {
> -               compatible = "moxa,moxart-timer";
> -               reg = <0x98400000 0x42>;
> -               interrupts = <19 1>;
> -               clocks = <&coreclk>;
> -       };
> --
> 2.9.3
>

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#1644905 — [PATCH 3/8 v2] clocksource/drivers/fttmr010: Drop Gemini specifics

The Gemini now has a proper clock driver and a proper PCLK
assigned in its device tree. Drop the Gemini-specific hacks
to look up the system speed and rely on the clock framework
like everyone else.

Cc: Joel Stanley <joel@jms.id.au>
Tested-by: Jonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Added Jonas' Tested-by, no functional changes.
---
 drivers/clocksource/timer-fttmr010.c | 103 ++++++++---------------------------
 1 file changed, 22 insertions(+), 81 deletions(-)

diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c
index 58ce017e4a65..db097db346e3 100644
--- a/drivers/clocksource/timer-fttmr010.c
+++ b/drivers/clocksource/timer-fttmr010.c
@@ -11,8 +11,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/regmap.h>
 #include <linux/clockchips.h>
 #include <linux/clocksource.h>
 #include <linux/sched_clock.h>
@@ -179,9 +177,28 @@ static struct irqaction fttmr010_timer_irq = {
 	.handler	= fttmr010_timer_interrupt,
 };
 
-static int __init fttmr010_timer_common_init(struct device_node *np)
+static int __init fttmr010_timer_init(struct device_node *np)
 {
 	int irq;
+	struct clk *clk;
+	int ret;
+
+	/*
+	 * These implementations require a clock reference.
+	 * FIXME: we currently only support clocking using PCLK
+	 * and using EXTCLK is not supported in the driver.
+	 */
+	clk = of_clk_get_by_name(np, "PCLK");
+	if (IS_ERR(clk)) {
+		pr_err("could not get PCLK\n");
+		return PTR_ERR(clk);
+	}
+	ret = clk_prepare_enable(clk);
+	if (ret) {
+		pr_err("failed to enable PCLK\n");
+		return ret;
+	}
+	tick_rate = clk_get_rate(clk);
 
 	base = of_iomap(np, 0);
 	if (!base) {
@@ -229,81 +246,5 @@ static int __init fttmr010_timer_common_init(struct device_node *np)
 
 	return 0;
 }
-
-static int __init fttmr010_timer_of_init(struct device_node *np)
-{
-	/*
-	 * These implementations require a clock reference.
-	 * FIXME: we currently only support clocking using PCLK
-	 * and using EXTCLK is not supported in the driver.
-	 */
-	struct clk *clk;
-	int ret;
-
-	clk = of_clk_get_by_name(np, "PCLK");
-	if (IS_ERR(clk)) {
-		pr_err("could not get PCLK\n");
-		return PTR_ERR(clk);
-	}
-	ret = clk_prepare_enable(clk);
-	if (ret) {
-		pr_err("failed to enable PCLK\n");
-		return ret;
-	}
-	tick_rate = clk_get_rate(clk);
-
-	return fttmr010_timer_common_init(np);
-}
-CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init);
-
-/*
- * Gemini-specific: relevant registers in the global syscon
- */
-#define GLOBAL_STATUS		0x04
-#define CPU_AHB_RATIO_MASK	(0x3 << 18)
-#define CPU_AHB_1_1		(0x0 << 18)
-#define CPU_AHB_3_2		(0x1 << 18)
-#define CPU_AHB_24_13		(0x2 << 18)
-#define CPU_AHB_2_1		(0x3 << 18)
-#define REG_TO_AHB_SPEED(reg)	((((reg) >> 15) & 0x7) * 10 + 130)
-
-static int __init gemini_timer_of_init(struct device_node *np)
-{
-	static struct regmap *map;
-	int ret;
-	u32 val;
-
-	map = syscon_regmap_lookup_by_phandle(np, "syscon");
-	if (IS_ERR(map)) {
-		pr_err("Can't get regmap for syscon handle\n");
-		return -ENODEV;
-	}
-	ret = regmap_read(map, GLOBAL_STATUS, &val);
-	if (ret) {
-		pr_err("Can't read syscon status register\n");
-		return -ENXIO;
-	}
-
-	tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
-	pr_info("Bus: %dMHz ", tick_rate / 1000000);
-
-	tick_rate /= 6;		/* APB bus run AHB*(1/6) */
-
-	switch (val & CPU_AHB_RATIO_MASK) {
-	case CPU_AHB_1_1:
-		pr_cont("(1/1)\n");
-		break;
-	case CPU_AHB_3_2:
-		pr_cont("(3/2)\n");
-		break;
-	case CPU_AHB_24_13:
-		pr_cont("(24/13)\n");
-		break;
-	case CPU_AHB_2_1:
-		pr_cont("(2/1)\n");
-		break;
-	}
-
-	return fttmr010_timer_common_init(np);
-}
-CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init);
+CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
+CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
-- 
2.9.3

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