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| Started by | Eric Anholt <eric@anholt.net> |
|---|---|
| First post | 2017-05-15 19:40 +0200 |
| Last post | 2017-05-15 21:10 +0200 |
| Articles | 3 — 2 participants |
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[PATCH] clk: bcm2835: Correct the prediv logic Eric Anholt <eric@anholt.net> - 2017-05-15 19:40 +0200
Re: [PATCH] clk: bcm2835: Correct the prediv logic Stefan Wahren <stefan.wahren@i2se.com> - 2017-05-15 19:50 +0200
Re: [PATCH] clk: bcm2835: Correct the prediv logic Eric Anholt <eric@anholt.net> - 2017-05-15 21:10 +0200
| From | Eric Anholt <eric@anholt.net> |
|---|---|
| Date | 2017-05-15 19:40 +0200 |
| Subject | [PATCH] clk: bcm2835: Correct the prediv logic |
| Message-ID | <tHs8p-2IK-1@gated-at.bofh.it> |
From: Phil Elwell <phil@raspberrypi.org>
If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
While this is a bugfix, I haven't put a "Fixes:" line in here to get
it automatically backported to stable. We had trouble with the
out-of-tree DSI panel driver, at least: Our old set_rate() didn't
work, because the new PLL was just barely too fast to get the integer
PLL divider we needed. We may run into similar troubles
elsewhere. --anholt
drivers/clk/bcm/clk-bcm2835.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 025853870619..7a35df6b45bd 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -616,8 +616,10 @@ static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
data->ana->fb_prediv_mask;
- if (using_prediv)
+ if (using_prediv) {
ndiv *= 2;
+ fdiv *= 2;
+ }
return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
}
--
2.11.0
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| From | Stefan Wahren <stefan.wahren@i2se.com> |
|---|---|
| Date | 2017-05-15 19:50 +0200 |
| Message-ID | <tHsi7-2M0-21@gated-at.bofh.it> |
| In reply to | #1641922 |
Hi Eric, > Eric Anholt <eric@anholt.net> hat am 15. Mai 2017 um 19:35 geschrieben: > > > From: Phil Elwell <phil@raspberrypi.org> > > If a clock has the prediv flag set, both the integer and fractional > parts must be scaled when calculating the resulting frequency. > > Signed-off-by: Phil Elwell <phil@raspberrypi.org> > Signed-off-by: Eric Anholt <eric@anholt.net> > --- > > While this is a bugfix, I haven't put a "Fixes:" line in here to get > it automatically backported to stable. sorry, i can't follow. How should this happen without "Fixes: "? > We had trouble with the > out-of-tree DSI panel driver, at least: Our old set_rate() didn't > work, because the new PLL was just barely too fast to get the integer > PLL divider we needed. We may run into similar troubles > elsewhere. --anholt >
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| From | Eric Anholt <eric@anholt.net> |
|---|---|
| Date | 2017-05-15 21:10 +0200 |
| Message-ID | <tHtxx-3GH-25@gated-at.bofh.it> |
| In reply to | #1641933 |
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Stefan Wahren <stefan.wahren@i2se.com> writes: > Hi Eric, > >> Eric Anholt <eric@anholt.net> hat am 15. Mai 2017 um 19:35 geschrieben: >> >> >> From: Phil Elwell <phil@raspberrypi.org> >> >> If a clock has the prediv flag set, both the integer and fractional >> parts must be scaled when calculating the resulting frequency. >> >> Signed-off-by: Phil Elwell <phil@raspberrypi.org> >> Signed-off-by: Eric Anholt <eric@anholt.net> >> --- >> >> While this is a bugfix, I haven't put a "Fixes:" line in here to get >> it automatically backported to stable. > > sorry, i can't follow. How should this happen without "Fixes: "? I didn't want it to be backported to stable, because of the risk.
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