Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1635603 > unrolled thread
| Started by | Ryder Lee <ryder.lee@mediatek.com> |
|---|---|
| First post | 2017-05-04 11:40 +0200 |
| Last post | 2017-05-08 18:30 +0200 |
| Articles | 2 — 2 participants |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
[PATCH v1 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY Ryder Lee <ryder.lee@mediatek.com> - 2017-05-04 11:40 +0200
Re: [PATCH v1 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY Rob Herring <robh@kernel.org> - 2017-05-08 18:30 +0200
| From | Ryder Lee <ryder.lee@mediatek.com> |
|---|---|
| Date | 2017-05-04 11:40 +0200 |
| Subject | [PATCH v1 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY |
| Message-ID | <tDloS-1BT-27@gated-at.bofh.it> |
Add documentation for PCIe PHY available in MT7623 series SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
.../devicetree/bindings/phy/phy-mt7623-pcie.txt | 63 ++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt
new file mode 100644
index 0000000..1309500
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt
@@ -0,0 +1,63 @@
+Mediatek MT7623 PCIe PHY
+-----------------------
+
+Required properties:
+ - compatible: Should contain "mediatek,mt7623-pcie-phy".
+ - reg: Base address and length of the registers.
+ - clocks: Must contain an entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "pciephya_ref"
+ - #phy-cells: Must be 0.
+
+Optional properties:
+ - mediatek,phy-switch: A phandle to the system controller, used to
+ switch the PHY on PCIe port2 which is shared with USB u3phy2.
+
+Example:
+
+ pcie0_phy: pcie-phy@1a149000 {
+ compatible = "mediatek,mt7623-pcie-phy";
+ reg = <0 0x1a149000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-names = "pciephya_ref";
+ #phy-cells = <0>;
+ };
+
+ pcie1_phy: pcie-phy@1a14a000 {
+ compatible = "mediatek,mt7623-pcie-phy";
+ reg = <0 0x1a14a000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-names = "pciephya_ref";
+ #phy-cells = <0>;
+ };
+
+ pcie2_phy: pcie-phy@1a244000 {
+ compatible = "mediatek,mt7623-pcie-phy";
+ reg = <0 0x1a244000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-names = "pciephya_ref";
+ #phy-cells = <0>;
+
+ mediatek,phy-switch = <&hifsys>;
+ };
+
+Specifying phy control of devices
+---------------------------------
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy node and phy-names.
+
+Example:
+
+#include <dt-bindings/phy/phy.h>
+
+pcie: pcie@1a140000 {
+ ...
+ pcie@1,0 {
+ ...
+ phys = <&pcie0_phy>;
+ phy-names = "pcie-phy0";
+ }
+ ...
+};
+
--
1.9.1
[toc] | [next] | [standalone]
| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2017-05-08 18:30 +0200 |
| Subject | Re: [PATCH v1 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY |
| Message-ID | <tETHQ-6g8-15@gated-at.bofh.it> |
| In reply to | #1635603 |
On Thu, May 04, 2017 at 05:31:48PM +0800, Ryder Lee wrote: > Add documentation for PCIe PHY available in MT7623 series SoCs. > > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > --- > .../devicetree/bindings/phy/phy-mt7623-pcie.txt | 63 ++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt Acked-by: Rob Herring <robh@kernel.org>
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web