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Groups > linux.kernel > #1634705 > unrolled thread

[PATCH v2 0/8] clk: sunxi-ng: Add support for A83T CCU

Started byChen-Yu Tsai <wens@csie.org>
First post2017-05-03 05:20 +0200
Last post2017-05-05 08:50 +0200
Articles 9 — 3 participants

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Contents

  [PATCH v2 0/8] clk: sunxi-ng: Add support for A83T CCU Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
    [PATCH v2 8/8] ARM: sun8i: a83t: Switch to CCU device tree binding macros Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
    [PATCH v2 4/8] clk: sunxi-ng: Support multiple variable pre-dividers Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
    [PATCH v2 2/8] clk: Provide option to query hardware for clk phase Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
    [PATCH v2 6/8] ARM: sun8i: a83t: Add CCU device nodes Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
    [PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
      Re: [PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible  string for A83T CCU Rob Herring <robh@kernel.org> - 2017-05-08 18:20 +0200
    [PATCH v2 7/8] ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator Chen-Yu Tsai <wens@csie.org> - 2017-05-03 05:20 +0200
    Re: [linux-sunxi] [PATCH v2 0/8] clk: sunxi-ng: Add support for A83T  CCU Corentin Labbe <clabbe.montjoie@gmail.com> - 2017-05-05 08:50 +0200

#1634705 — [PATCH v2 0/8] clk: sunxi-ng: Add support for A83T CCU

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 0/8] clk: sunxi-ng: Add support for A83T CCU
Message-ID<tCSZz-7mp-3@gated-at.bofh.it>
Hi everyone,

(Resent with devicetree mailing list CC-ed.)
This is v2 of my A83T CCU series. This is for 4.13.

Changes since v1:

  - Dropped two patches that were merged

  - Added clk core flag to disable caching of clock phases

  - Added support for multiple variable pre-dividers

  - Merged "pll-periph-ahb1" pre-divider clock into "ahb1" clock
    with multiple variable pre-dividers

  - Introduced new class of phase clocks that return -ENOTSUPP
    when the clock is in new timing mode

  - Force mmc2 clock to new timing mode

  - Added back mmc2 output and sample clocks

  - Fixed bit ops for forcing audio PLL configuration

  - Added requirement for "losc" clock in device tree binding

  - Stripped leading 0 in device node name

  - Updated subject prefixes for various patches

Patch 1 adds a compatible string for the A83T CCU to the sunxi-ccu
bindings.

Patch 2 adds a CLK_GET_PHASE_NOCACHE flag to the clk core, asking it
not to cache clock phase values. This is similar to CLK_GET_RATE_NOCACHE.
Patch 5 has a compile time dependency on this patch, for the flag value.

Patch 3 adds a new class of phase clocks that check the new timing mode
bit, and returns an error if it is set, which indicates the phase delays
no longer apply. This is a clean way to signal which timing mode the mmc
clock is in, without using any custom functions or callbacks. We don't
support runtime switching of modes.

Patch 4 adds support for multiple variable pre-dividers to the sunxi-ng
mux class.

Patch 5 adds the driver for the A83T CCU.

Patch 6 adds the CCU device nodes, and fixes up any existing clock
phandles in the dtsi, without using the macros.

Patch 7 sets the clock accuracy for the main oscillator.

Patch 8 is for the next -rc2, switch the clock indices from raw numbers
to macros we introduced with the driver. This will be updated if more
peripherals are introduced in the same cycle.

Let me know what you think.

Cover letter excerpt from v1:

This is yet another series that adds support for the A83T CCU.
The A83T CCU has a mix of new styled (like the A80) clocks at
old (like A3x) offsets. Some differences include:

  - D1/D2 style PLL clocks
  - divisible audio module clocks
  - new timing mode for mmc2 module clock


Regards
ChenYu

Chen-Yu Tsai (8):
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
  clk: Provide option to query hardware for clk phase
  clk: sunxi-ng: Add class of phase clocks supporting MMC new timing
    modes
  clk: sunxi-ng: Support multiple variable pre-dividers
  clk: sunxi-ng: Add driver for A83T CCU
  ARM: sun8i: a83t: Add CCU device nodes
  ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator
  ARM: sun8i: a83t: Switch to CCU device tree binding macros

 .../devicetree/bindings/clock/sunxi-ccu.txt        |   2 +
 arch/arm/boot/dts/sun8i-a83t.dtsi                  |  19 +-
 drivers/clk/clk.c                                  |   6 +-
 drivers/clk/sunxi-ng/Kconfig                       |  10 +
 drivers/clk/sunxi-ng/Makefile                      |   1 +
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c              |  10 +-
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c               |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-a23.c               |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c               |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c              | 911 +++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h              |  64 ++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c                |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-r.c                 |  10 +-
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c               |  10 +-
 drivers/clk/sunxi-ng/ccu_mux.c                     |  15 +-
 drivers/clk/sunxi-ng/ccu_mux.h                     |  13 +-
 drivers/clk/sunxi-ng/ccu_phase.c                   |  47 ++
 drivers/clk/sunxi-ng/ccu_phase.h                   |  16 +
 include/dt-bindings/clock/sun8i-a83t-ccu.h         | 140 ++++
 include/dt-bindings/reset/sun8i-a83t-ccu.h         |  98 +++
 include/linux/clk-provider.h                       |   1 +
 21 files changed, 1363 insertions(+), 50 deletions(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
 create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h

-- 
2.11.0

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#1634706 — [PATCH v2 8/8] ARM: sun8i: a83t: Switch to CCU device tree binding macros

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 8/8] ARM: sun8i: a83t: Switch to CCU device tree binding macros
Message-ID<tCSZz-7mp-7@gated-at.bofh.it>
In reply to#1634705
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index e12dd7170b8f..050d3e347740 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -44,6 +44,9 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
+#include <dt-bindings/reset/sun8i-a83t-ccu.h>
+
 / {
 	interrupt-parent = <&gic>;
 	#address-cells = <1>;
@@ -178,7 +181,7 @@
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x01c20800 0x400>;
-			clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
@@ -225,8 +228,8 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&ccu 53>;
-			resets = <&ccu 40>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
 			status = "disabled";
 		};
 
-- 
2.11.0

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#1634708 — [PATCH v2 4/8] clk: sunxi-ng: Support multiple variable pre-dividers

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 4/8] clk: sunxi-ng: Support multiple variable pre-dividers
Message-ID<tCSZz-7mp-11@gated-at.bofh.it>
In reply to#1634705
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.

As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-a23.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c   | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-r.c    | 10 +++++-----
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c  | 10 +++++-----
 drivers/clk/sunxi-ng/ccu_mux.c        | 15 ++++++++-------
 drivers/clk/sunxi-ng/ccu_mux.h        | 13 ++++++++-----
 9 files changed, 51 insertions(+), 47 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index f54114c607df..2bb4cabf802f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -211,6 +211,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -218,11 +221,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 89e68d29bf45..bc9f2ca19233 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -195,6 +195,9 @@ static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi", "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -203,11 +206,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index 5c6d37bdf247..8a753ed0426d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -169,6 +169,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -176,11 +179,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 8d38e6510e29..10b38dc46f75 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -180,6 +180,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi" , "pll-periph" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -187,11 +190,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..62e4f0d2b2fc 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -141,6 +141,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi" , "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -148,11 +151,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index 119f47b568ea..de02be75785c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -27,6 +27,9 @@
 
 static const char * const ar100_parents[] = { "osc32k", "osc24M",
 					     "pll-periph0", "iosc" };
+static const struct ccu_mux_var_prediv ar100_predivs[] = {
+	{ .index = 2, .shift = 8, .width = 5 },
+};
 
 static struct ccu_div ar100_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
@@ -35,11 +38,8 @@ static struct ccu_div ar100_clk = {
 		.shift	= 16,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 2,
-			.shift	= 8,
-			.width	= 5,
-		},
+		.var_predivs	= ar100_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ar100_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index e58706b40ae9..cb7299a94cba 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -132,6 +132,9 @@ static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
 
 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 					     "axi", "pll-periph0" };
+static const struct ccu_mux_var_prediv ahb1_predivs[] = {
+	{ .index = 3, .shift = 6, .width = 2 },
+};
 static struct ccu_div ahb1_clk = {
 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 
@@ -139,11 +142,8 @@ static struct ccu_div ahb1_clk = {
 		.shift	= 12,
 		.width	= 2,
 
-		.variable_prediv	= {
-			.index	= 3,
-			.shift	= 6,
-			.width	= 2,
-		},
+		.var_predivs	= ahb1_predivs,
+		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
 	},
 
 	.common		= {
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index c6bb1f523232..b1eaafac9f23 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -46,13 +46,14 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
 				prediv = cm->fixed_predivs[i].div;
 
 	if (common->features & CCU_FEATURE_VARIABLE_PREDIV)
-		if (parent_index == cm->variable_prediv.index) {
-			u8 div;
-
-			div = reg >> cm->variable_prediv.shift;
-			div &= (1 << cm->variable_prediv.width) - 1;
-			prediv = div + 1;
-		}
+		for (i = 0; i < cm->n_var_predivs; i++)
+			if (parent_index == cm->var_predivs[i].index) {
+				u8 div;
+
+				div = reg >> cm->var_predivs[i].shift;
+				div &= (1 << cm->var_predivs[i].width) - 1;
+				prediv = div + 1;
+			}
 
 	*parent_rate = *parent_rate / prediv;
 }
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index 47aba3a48245..044262245c07 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -10,6 +10,12 @@ struct ccu_mux_fixed_prediv {
 	u16	div;
 };
 
+struct ccu_mux_var_prediv {
+	u8	index;
+	u8	shift;
+	u8	width;
+};
+
 struct ccu_mux_internal {
 	u8		shift;
 	u8		width;
@@ -18,11 +24,8 @@ struct ccu_mux_internal {
 	const struct ccu_mux_fixed_prediv	*fixed_predivs;
 	u8		n_predivs;
 
-	struct {
-		u8	index;
-		u8	shift;
-		u8	width;
-	} variable_prediv;
+	const struct ccu_mux_var_prediv		*var_predivs;
+	u8		n_var_predivs;
 };
 
 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table)	\
-- 
2.11.0

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#1634710 — [PATCH v2 2/8] clk: Provide option to query hardware for clk phase

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 2/8] clk: Provide option to query hardware for clk phase
Message-ID<tCSZz-7mp-13@gated-at.bofh.it>
In reply to#1634705
On some hardware, the clk phase is tied to the parent clk's
rate and some clk delay programmed into the hardware. As the
parent clk rate changes, so does the clk phase.

Add a clk flag specifying not to use the cached clk phase,
but always query the hardware for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/clk.c            | 6 +++++-
 include/linux/clk-provider.h | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 67201f67a14a..05e2481c1340 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1929,7 +1929,11 @@ static int clk_core_get_phase(struct clk_core *core)
 	int ret;
 
 	clk_prepare_lock();
-	ret = core->phase;
+	if (core && (core->flags & CLK_GET_PHASE_NOCACHE) &&
+	    core->ops->get_phase)
+		ret = core->ops->get_phase(core->hw);
+	else
+		ret = core->phase;
 	clk_prepare_unlock();
 
 	return ret;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a428aec36ace..e2e856b1a81f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -35,6 +35,7 @@
 #define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
 /* parents need enable during gate/ungate, set rate and re-parent */
 #define CLK_OPS_PARENT_ENABLE	BIT(12)
+#define CLK_GET_PHASE_NOCACHE	BIT(13) /* do not use the cached clk phase */
 
 struct clk;
 struct clk_hw;
-- 
2.11.0

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#1634712 — [PATCH v2 6/8] ARM: sun8i: a83t: Add CCU device nodes

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 6/8] ARM: sun8i: a83t: Add CCU device nodes
Message-ID<tCSZz-7mp-17@gated-at.bofh.it>
In reply to#1634705
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c0a1e4f74b89..c9a5d07b2ada 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -162,13 +162,23 @@
 		#size-cells = <1>;
 		ranges;
 
+		ccu: clock@1c20000 {
+			compatible = "allwinner,sun8i-a83t-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc16Md512>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun8i-a83t-pinctrl";
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x01c20800 0x400>;
-			clocks = <&osc24M>;
+			clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
+			clock-names = "apb", "hosc", "losc";
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
@@ -214,7 +224,8 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&ccu 53>;
+			resets = <&ccu 40>;
 			status = "disabled";
 		};
 
-- 
2.11.0

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#1634715 — [PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
Message-ID<tCSZA-7mp-23@gated-at.bofh.it>
In reply to#1634705
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.

Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index e9c5a1d9834a..34b2a9249a94 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -6,6 +6,7 @@ Required properties :
 		- "allwinner,sun6i-a31-ccu"
 		- "allwinner,sun8i-a23-ccu"
 		- "allwinner,sun8i-a33-ccu"
+		- "allwinner,sun8i-a83t-ccu"
 		- "allwinner,sun8i-h3-ccu"
 		- "allwinner,sun8i-h3-r-ccu"
 		- "allwinner,sun8i-v3s-ccu"
@@ -18,6 +19,7 @@ Required properties :
 - clocks: phandle to the oscillators feeding the CCU. Two are needed:
   - "hosc": the high frequency oscillator (usually at 24MHz)
   - "losc": the low frequency oscillator (usually at 32kHz)
+	    On the A83T, this is the internal 16MHz oscillator divided by 512
 - clock-names: Must contain the clock names described just above
 - #clock-cells : must contain 1
 - #reset-cells : must contain 1
-- 
2.11.0

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#1637550 — Re: [PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU

FromRob Herring <robh@kernel.org>
Date2017-05-08 18:20 +0200
SubjectRe: [PATCH v2 1/8] dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
Message-ID<tETya-6cU-11@gated-at.bofh.it>
In reply to#1634715
On Wed, May 03, 2017 at 11:16:51AM +0800, Chen-Yu Tsai wrote:
> The A83T clock control unit is a hybrid of some new style clock designs
> from the A80, and old style layout from the other Allwinner SoCs.
> 
> Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
> Unlike the A80, there is no clock input either. The only low speed clock
> available is the internal oscillator which runs at around 16 MHz,
> divided by 512, yielding a low speed clock around 31.250 kHz.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

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#1634717 — [PATCH v2 7/8] ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator

FromChen-Yu Tsai <wens@csie.org>
Date2017-05-03 05:20 +0200
Subject[PATCH v2 7/8] ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator
Message-ID<tCSZA-7mp-25@gated-at.bofh.it>
In reply to#1634705
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c9a5d07b2ada..e12dd7170b8f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -126,6 +126,7 @@
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
+			clock-accuracy = <50000>;
 			clock-output-names = "osc24M";
 		};
 
-- 
2.11.0

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#1636195 — Re: [linux-sunxi] [PATCH v2 0/8] clk: sunxi-ng: Add support for A83T CCU

FromCorentin Labbe <clabbe.montjoie@gmail.com>
Date2017-05-05 08:50 +0200
SubjectRe: [linux-sunxi] [PATCH v2 0/8] clk: sunxi-ng: Add support for A83T CCU
Message-ID<tDFdU-6v3-7@gated-at.bofh.it>
In reply to#1634705
On Wed, May 03, 2017 at 11:16:50AM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> (Resent with devicetree mailing list CC-ed.)
> This is v2 of my A83T CCU series. This is for 4.13.
> 
> Changes since v1:
> 
>   - Dropped two patches that were merged
> 
>   - Added clk core flag to disable caching of clock phases
> 
>   - Added support for multiple variable pre-dividers
> 
>   - Merged "pll-periph-ahb1" pre-divider clock into "ahb1" clock
>     with multiple variable pre-dividers
> 
>   - Introduced new class of phase clocks that return -ENOTSUPP
>     when the clock is in new timing mode
> 
>   - Force mmc2 clock to new timing mode
> 
>   - Added back mmc2 output and sample clocks
> 
>   - Fixed bit ops for forcing audio PLL configuration
> 
>   - Added requirement for "losc" clock in device tree binding
> 
>   - Stripped leading 0 in device node name
> 
>   - Updated subject prefixes for various patches
> 
> Patch 1 adds a compatible string for the A83T CCU to the sunxi-ccu
> bindings.
> 
> Patch 2 adds a CLK_GET_PHASE_NOCACHE flag to the clk core, asking it
> not to cache clock phase values. This is similar to CLK_GET_RATE_NOCACHE.
> Patch 5 has a compile time dependency on this patch, for the flag value.
> 
> Patch 3 adds a new class of phase clocks that check the new timing mode
> bit, and returns an error if it is set, which indicates the phase delays
> no longer apply. This is a clean way to signal which timing mode the mmc
> clock is in, without using any custom functions or callbacks. We don't
> support runtime switching of modes.
> 
> Patch 4 adds support for multiple variable pre-dividers to the sunxi-ng
> mux class.
> 
> Patch 5 adds the driver for the A83T CCU.
> 
> Patch 6 adds the CCU device nodes, and fixes up any existing clock
> phandles in the dtsi, without using the macros.
> 
> Patch 7 sets the clock accuracy for the main oscillator.
> 
> Patch 8 is for the next -rc2, switch the clock indices from raw numbers
> to macros we introduced with the driver. This will be updated if more
> peripherals are introduced in the same cycle.
> 
> Let me know what you think.
> 
> Cover letter excerpt from v1:
> 
> This is yet another series that adds support for the A83T CCU.
> The A83T CCU has a mix of new styled (like the A80) clocks at
> old (like A3x) offsets. Some differences include:
> 
>   - D1/D2 style PLL clocks
>   - divisible audio module clocks
>   - new timing mode for mmc2 module clock
> 
> 
> Regards
> ChenYu
> 
> Chen-Yu Tsai (8):
>   dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
>   clk: Provide option to query hardware for clk phase
>   clk: sunxi-ng: Add class of phase clocks supporting MMC new timing
>     modes
>   clk: sunxi-ng: Support multiple variable pre-dividers
>   clk: sunxi-ng: Add driver for A83T CCU
>   ARM: sun8i: a83t: Add CCU device nodes
>   ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillator
>   ARM: sun8i: a83t: Switch to CCU device tree binding macros
> 
>  .../devicetree/bindings/clock/sunxi-ccu.txt        |   2 +
>  arch/arm/boot/dts/sun8i-a83t.dtsi                  |  19 +-
>  drivers/clk/clk.c                                  |   6 +-
>  drivers/clk/sunxi-ng/Kconfig                       |  10 +
>  drivers/clk/sunxi-ng/Makefile                      |   1 +
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c              |  10 +-
>  drivers/clk/sunxi-ng/ccu-sun6i-a31.c               |  10 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-a23.c               |  10 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-a33.c               |  10 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-a83t.c              | 911 +++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-sun8i-a83t.h              |  64 ++
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c                |  10 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-r.c                 |  10 +-
>  drivers/clk/sunxi-ng/ccu-sun8i-v3s.c               |  10 +-
>  drivers/clk/sunxi-ng/ccu_mux.c                     |  15 +-
>  drivers/clk/sunxi-ng/ccu_mux.h                     |  13 +-
>  drivers/clk/sunxi-ng/ccu_phase.c                   |  47 ++
>  drivers/clk/sunxi-ng/ccu_phase.h                   |  16 +
>  include/dt-bindings/clock/sun8i-a83t-ccu.h         | 140 ++++
>  include/dt-bindings/reset/sun8i-a83t-ccu.h         |  98 +++
>  include/linux/clk-provider.h                       |   1 +
>  21 files changed, 1363 insertions(+), 50 deletions(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
>  create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h
> 

Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>

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