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[tip:perf/core] perf vendor events intel: Add uncore events for Xeon Phi (Knights Landing)

Started bytip-bot for Andi Kleen <tipbot@zytor.com>
First post2017-02-10 09:00 +0100
Last post2017-02-10 09:00 +0100
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  [tip:perf/core] perf vendor events intel: Add uncore events for  Xeon Phi (Knights Landing) tip-bot for Andi Kleen <tipbot@zytor.com> - 2017-02-10 09:00 +0100

#1578242 — [tip:perf/core] perf vendor events intel: Add uncore events for Xeon Phi (Knights Landing)

Fromtip-bot for Andi Kleen <tipbot@zytor.com>
Date2017-02-10 09:00 +0100
Subject[tip:perf/core] perf vendor events intel: Add uncore events for Xeon Phi (Knights Landing)
Message-ID<t9ehz-xE-1@gated-at.bofh.it>
Commit-ID:  22c8e5526b7bf33840c20b4e717e6560e5dfb294
Gitweb:     http://git.kernel.org/tip/22c8e5526b7bf33840c20b4e717e6560e5dfb294
Author:     Andi Kleen <ak@linux.intel.com>
AuthorDate: Mon, 19 Sep 2016 09:36:31 -0700
Committer:  Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Wed, 8 Feb 2017 16:38:03 -0300

perf vendor events intel: Add uncore events for Xeon Phi (Knights Landing)

Add metrics for memory and MCDRAM. Minimal metrics only for now.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: http://lkml.kernel.org/n/tip-c0cix4eprbldfrx5zf60suvh@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
 .../arch/x86/knightslanding/uncore-memory.json     | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json
new file mode 100644
index 0000000..e3bcd86
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json
@@ -0,0 +1,42 @@
+[
+    {
+        "BriefDescription": "ddr bandwidth read (CPU traffic only) (MB/sec). ",
+        "Counter": "0,1,2,3",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_CAS_COUNT.RD",
+        "PerPkg": "1",
+        "ScaleUnit": "6.4e-05MiB",
+        "UMask": "0x01",
+        "Unit": "imc"
+    },
+    {
+        "BriefDescription": "ddr bandwidth write (CPU traffic only) (MB/sec). ",
+        "Counter": "0,1,2,3",
+        "EventCode": "0x03",
+        "EventName": "UNC_M_CAS_COUNT.WR",
+        "PerPkg": "1",
+        "ScaleUnit": "6.4e-05MiB",
+        "UMask": "0x02",
+        "Unit": "imc"
+    },
+    {
+        "BriefDescription": "mcdram bandwidth read (CPU traffic only) (MB/sec). ",
+        "Counter": "0,1,2,3",
+        "EventCode": "0x01",
+        "EventName": "UNC_E_RPQ_INSERTS",
+        "PerPkg": "1",
+        "ScaleUnit": "6.4e-05MiB",
+        "UMask": "0x01",
+        "Unit": "edc_eclk"
+    },
+    {
+        "BriefDescription": "mcdram bandwidth write (CPU traffic only) (MB/sec). ",
+        "Counter": "0,1,2,3",
+        "EventCode": "0x02",
+        "EventName": "UNC_E_WPQ_INSERTS",
+        "PerPkg": "1",
+        "ScaleUnit": "6.4e-05MiB",
+        "UMask": "0x01",
+        "Unit": "edc_eclk"
+    }
+]

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