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[PATCH] x86, perf: Add Top Down events to Intel Goldmont

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  [PATCH] x86, perf: Add Top Down events to Intel Goldmont kan.liang@intel.com - 2017-02-09 22:40 +0100
    Re: [PATCH] x86, perf: Add Top Down events to Intel Goldmont Ingo Molnar <mingo@kernel.org> - 2017-02-10 10:00 +0100

#1577973 — [PATCH] x86, perf: Add Top Down events to Intel Goldmont

From: Kan Liang <kan.liang@intel.com>

Goldmont supports full Top Down level 1 metrics (FrontendBound,
Retiring, Backend Bound and Bad Speculation).
It has 3 wide pipeline.

Signed-off-by: Kan Liang <kan.liang@intel.com>
---
 arch/x86/events/intel/core.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index eb1484c..baaac28 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -1553,6 +1553,31 @@ static __initconst const u64 slm_hw_cache_event_ids
  },
 };
 
+EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
+EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
+/* UOPS_NOT_DELIVERED.ANY */
+EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm,
+	       "event=0x9c");
+/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
+EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm,
+	       "event=0xca,umask=0x02");
+/* UOPS_RETIRED.ANY */
+EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm,
+	       "event=0xc2");
+/* UOPS_ISSUED.ANY */
+EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm,
+	       "event=0x0e");
+
+static struct attribute *glm_events_attrs[] = {
+	EVENT_PTR(td_total_slots_glm),
+	EVENT_PTR(td_total_slots_scale_glm),
+	EVENT_PTR(td_fetch_bubbles_glm),
+	EVENT_PTR(td_recovery_bubbles_glm),
+	EVENT_PTR(td_slots_issued_glm),
+	EVENT_PTR(td_slots_retired_glm),
+	NULL
+};
+
 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
 	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
@@ -3750,6 +3775,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_prec_dist = true;
 		x86_pmu.lbr_pt_coexist = true;
 		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
+		x86_pmu.cpu_events = glm_events_attrs;
 		pr_cont("Goldmont events, ");
 		break;
 
-- 
2.4.3

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#1578311

* kan.liang@intel.com <kan.liang@intel.com> wrote:

> From: Kan Liang <kan.liang@intel.com>
> 
> Goldmont supports full Top Down level 1 metrics (FrontendBound,
> Retiring, Backend Bound and Bad Speculation).
> It has 3 wide pipeline.
> 
> Signed-off-by: Kan Liang <kan.liang@intel.com>
> ---
>  arch/x86/events/intel/core.c | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index eb1484c..baaac28 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -1553,6 +1553,31 @@ static __initconst const u64 slm_hw_cache_event_ids
>   },
>  };
>  
> +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
> +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
> +/* UOPS_NOT_DELIVERED.ANY */
> +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm,
> +	       "event=0x9c");
> +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
> +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm,
> +	       "event=0xca,umask=0x02");
> +/* UOPS_RETIRED.ANY */
> +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm,
> +	       "event=0xc2");
> +/* UOPS_ISSUED.ANY */
> +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm,
> +	       "event=0x0e");

Please don't
                                                        break lines
in funny places and make code
                                                  unreadable.

Instead have a look at the existing event listing style in 
arch/x86/events/intel/core.c and match that!

Ok?

Thanks,

	Ingo

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