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[PATCH v5 0/6] Rockchip dw-mipi-dsi driver

Started byChris Zhong <zyw@rock-chips.com>
First post2017-02-05 05:00 +0100
Last post2017-02-07 17:20 +0100
Articles 4 — 2 participants

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Contents

  [PATCH v5 0/6] Rockchip dw-mipi-dsi driver Chris Zhong <zyw@rock-chips.com> - 2017-02-05 05:00 +0100
    [PATCH v5 5/6] dt-bindings: add power domain node for dw-mipi-rockchip Chris Zhong <zyw@rock-chips.com> - 2017-02-05 05:00 +0100
    [PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi Chris Zhong <zyw@rock-chips.com> - 2017-02-05 05:00 +0100
      Re: [PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi Sean Paul <seanpaul@chromium.org> - 2017-02-07 17:20 +0100

#1573808 — [PATCH v5 0/6] Rockchip dw-mipi-dsi driver

FromChris Zhong <zyw@rock-chips.com>
Date2017-02-05 05:00 +0100
Subject[PATCH v5 0/6] Rockchip dw-mipi-dsi driver
Message-ID<t7m9z-1Xc-3@gated-at.bofh.it>
Hi all

This patch serial is for RK3399 MIPI DSI. The MIPI DSI controller of
RK3399 is almost the same as RK3288, except a little bit of difference
in phy clock controlling and port id selection register. These patches
add RK3399 support and the power domain support.

And these patches base on John Keeping's series[0], it fixes many bugs,
they have been tested on rk3288 evb board.

[0]:
[01/26] https://patchwork.kernel.org/patch/9340213
[02/26] https://patchwork.kernel.org/patch/9340145
[03/26] https://patchwork.kernel.org/patch/9340235
[04/26] https://patchwork.kernel.org/patch/9340123
[05/26] https://patchwork.kernel.org/patch/9340161
[06/26] https://patchwork.kernel.org/patch/9340203
[07/26] https://patchwork.kernel.org/patch/9340229
[08/26] https://patchwork.kernel.org/patch/9340131
[09/26] https://patchwork.kernel.org/patch/9340191
[10/26] https://patchwork.kernel.org/patch/9340175
[11/26] https://patchwork.kernel.org/patch/9340237
[12/26] https://patchwork.kernel.org/patch/9340207
[13/26] https://patchwork.kernel.org/patch/9340233
[14/26] https://patchwork.kernel.org/patch/9340205
[15/26] https://patchwork.kernel.org/patch/9340189
[16/26] https://patchwork.kernel.org/patch/9340143
[17/26] https://patchwork.kernel.org/patch/9340117
[18/26] https://patchwork.kernel.org/patch/9340193
[19/26] https://patchwork.kernel.org/patch/9340151
[20/26] https://patchwork.kernel.org/patch/9340183
[23/26] https://patchwork.kernel.org/patch/9340173
[24/26] https://patchwork.kernel.org/patch/9340251
[25/26] https://patchwork.kernel.org/patch/9340127
[26/26] https://patchwork.kernel.org/patch/9340139


Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind

Changes in v4:
- remove the unrelated change

Changes in v3:
- base on John Keeping's patch series

Chris Zhong (6):
  dt-bindings: add rk3399 support for dw-mipi-rockchip
  drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
  drm/rockchip/dsi: dw-mipi: correct the coding style
  drm/rockchip/dsi: remove mode_valid function
  dt-bindings: add power domain node for dw-mipi-rockchip
  drm/rockchip/dsi: add dw-mipi power domain support

 .../display/rockchip/dw_mipi_dsi_rockchip.txt      |   7 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c             | 163 ++++++++++++---------
 2 files changed, 103 insertions(+), 67 deletions(-)

-- 
2.6.3

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#1573809 — [PATCH v5 5/6] dt-bindings: add power domain node for dw-mipi-rockchip

FromChris Zhong <zyw@rock-chips.com>
Date2017-02-05 05:00 +0100
Subject[PATCH v5 5/6] dt-bindings: add power domain node for dw-mipi-rockchip
Message-ID<t7m9z-1Xc-11@gated-at.bofh.it>
In reply to#1573808
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---

Changes in v5: None
Changes in v4: None
Changes in v3: None

 .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 0f82568..188f6f7 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -15,6 +15,9 @@ Required properties:
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
 
+Optional properties:
+- power-domains: a phandle to mipi dsi power domain node.
+
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
 
-- 
2.6.3

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#1573810 — [PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

FromChris Zhong <zyw@rock-chips.com>
Date2017-02-05 05:00 +0100
Subject[PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
Message-ID<t7m9A-1Xc-13@gated-at.bofh.it>
In reply to#1573808
The vopb/vopl switch register of RK3399 mipi is different from RK3288,
the default setting for mipi dsi mode is different too, so add a
of_device_id structure to distinguish them, and make sure set the
correct mode before mipi phy init.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

---

Changes in v5:
- check the error of phy_cfg_clk in dw_mipi_dsi_bind

Changes in v4:
- remove the unrelated change

Changes in v3:
- base on John Keeping's patch series

 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 75 +++++++++++++++++++++++++++++-----
 1 file changed, 65 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 45af890..7d337e2 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -29,9 +29,17 @@
 
 #define DRIVER_NAME    "dw-mipi-dsi"
 
-#define GRF_SOC_CON6                    0x025c
-#define DSI0_SEL_VOP_LIT                (1 << 6)
-#define DSI1_SEL_VOP_LIT                (1 << 9)
+#define RK3288_GRF_SOC_CON6		0x025c
+#define RK3288_DSI0_SEL_VOP_LIT		BIT(6)
+#define RK3288_DSI1_SEL_VOP_LIT		BIT(9)
+
+#define RK3399_GRF_SOC_CON19		0x6250
+#define RK3399_DSI0_SEL_VOP_LIT		BIT(0)
+#define RK3399_DSI1_SEL_VOP_LIT		BIT(4)
+
+/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
+#define RK3399_GRF_SOC_CON22		0x6258
+#define RK3399_GRF_DSI_MODE		0xffff0000
 
 #define DSI_VERSION			0x00
 #define DSI_PWR_UP			0x04
@@ -265,6 +273,11 @@ enum {
 };
 
 struct dw_mipi_dsi_plat_data {
+	u32 dsi0_en_bit;
+	u32 dsi1_en_bit;
+	u32 grf_switch_reg;
+	u32 grf_dsi0_mode;
+	u32 grf_dsi0_mode_reg;
 	unsigned int max_data_lanes;
 	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
 					   struct drm_display_mode *mode);
@@ -281,6 +294,7 @@ struct dw_mipi_dsi {
 
 	struct clk *pllref_clk;
 	struct clk *pclk;
+	struct clk *phy_cfg_clk;
 
 	unsigned int lane_mbps; /* per lane */
 	u32 channel;
@@ -426,6 +440,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 
+	if (dsi->phy_cfg_clk) {
+		ret = clk_prepare_enable(dsi->phy_cfg_clk);
+		if (ret) {
+			dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
+			return ret;
+		}
+	}
+
 	dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
 					 VCO_RANGE_CON_SEL(vco) |
 					 VCO_IN_CAP_CON_LOW |
@@ -479,17 +501,19 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 	if (ret < 0) {
 		dev_err(dsi->dev, "failed to wait for phy lock state\n");
-		return ret;
+		goto phy_init_end;
 	}
 
 	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 				 val, val & STOP_STATE_CLK_LANE, 1000,
 				 PHY_STATUS_TIMEOUT_US);
-	if (ret < 0) {
+	if (ret < 0)
 		dev_err(dsi->dev,
 			"failed to wait for phy clk lane stop state\n");
-		return ret;
-	}
+
+phy_init_end:
+	if (dsi->phy_cfg_clk)
+		clk_disable_unprepare(dsi->phy_cfg_clk);
 
 	return ret;
 }
@@ -965,6 +989,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 {
 	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
+	const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
 	int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 	u32 val;
 
@@ -985,6 +1010,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	dw_mipi_dsi_dphy_interface_config(dsi);
 	dw_mipi_dsi_clear_err(dsi);
 
+	if (pdata->grf_dsi0_mode_reg)
+		regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
+			     pdata->grf_dsi0_mode);
+
 	dw_mipi_dsi_phy_init(dsi);
 	dw_mipi_dsi_wait_for_two_frames(dsi);
 
@@ -998,11 +1027,11 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 	clk_disable_unprepare(dsi->pclk);
 
 	if (mux)
-		val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16);
+		val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
 	else
-		val = DSI0_SEL_VOP_LIT << 16;
+		val = pdata->dsi0_en_bit << 16;
 
-	regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val);
+	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
 	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
 }
 
@@ -1162,14 +1191,29 @@ static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
 }
 
 static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
+	.dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
+	.dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
+	.grf_switch_reg = RK3288_GRF_SOC_CON6,
 	.max_data_lanes = 4,
 	.mode_valid = rk3288_mipi_dsi_mode_valid,
 };
 
+static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
+	.dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
+	.dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
+	.grf_switch_reg = RK3399_GRF_SOC_CON19,
+	.grf_dsi0_mode = RK3399_GRF_DSI_MODE,
+	.grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
+	.max_data_lanes = 4,
+};
+
 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
 	{
 	 .compatible = "rockchip,rk3288-mipi-dsi",
 	 .data = &rk3288_mipi_dsi_drv_data,
+	}, {
+	 .compatible = "rockchip,rk3399-mipi-dsi",
+	 .data = &rk3399_mipi_dsi_drv_data,
 	},
 	{ /* sentinel */ }
 };
@@ -1249,6 +1293,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
 		clk_disable_unprepare(dsi->pclk);
 	}
 
+	dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
+	if (IS_ERR(dsi->phy_cfg_clk)) {
+		ret = PTR_ERR(dsi->phy_cfg_clk);
+		if (ret != -ENOENT) {
+			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
+			return ret;
+		}
+		dsi->phy_cfg_clk = NULL;
+		dev_dbg(dev, "have not phy_cfg_clk\n");
+	}
+
 	ret = clk_prepare_enable(dsi->pllref_clk);
 	if (ret) {
 		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
-- 
2.6.3

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#1575836 — Re: [PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi

FromSean Paul <seanpaul@chromium.org>
Date2017-02-07 17:20 +0100
SubjectRe: [PATCH v5 2/6] drm/rockchip/dsi: dw-mipi: support RK3399 mipi dsi
Message-ID<t8gEN-5ar-7@gated-at.bofh.it>
In reply to#1573810
On Sun, Feb 05, 2017 at 11:54:10AM +0800, Chris Zhong wrote:
> The vopb/vopl switch register of RK3399 mipi is different from RK3288,
> the default setting for mipi dsi mode is different too, so add a
> of_device_id structure to distinguish them, and make sure set the
> correct mode before mipi phy init.
> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
> 
> ---
> 
> Changes in v5:
> - check the error of phy_cfg_clk in dw_mipi_dsi_bind
> 
> Changes in v4:
> - remove the unrelated change
> 
> Changes in v3:
> - base on John Keeping's patch series
> 
>  drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 75 +++++++++++++++++++++++++++++-----
>  1 file changed, 65 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 45af890..7d337e2 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -29,9 +29,17 @@
>  
>  #define DRIVER_NAME    "dw-mipi-dsi"
>  
> -#define GRF_SOC_CON6                    0x025c
> -#define DSI0_SEL_VOP_LIT                (1 << 6)
> -#define DSI1_SEL_VOP_LIT                (1 << 9)
> +#define RK3288_GRF_SOC_CON6		0x025c
> +#define RK3288_DSI0_SEL_VOP_LIT		BIT(6)
> +#define RK3288_DSI1_SEL_VOP_LIT		BIT(9)
> +
> +#define RK3399_GRF_SOC_CON19		0x6250
> +#define RK3399_DSI0_SEL_VOP_LIT		BIT(0)
> +#define RK3399_DSI1_SEL_VOP_LIT		BIT(4)
> +
> +/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
> +#define RK3399_GRF_SOC_CON22		0x6258
> +#define RK3399_GRF_DSI_MODE		0xffff0000
>  
>  #define DSI_VERSION			0x00
>  #define DSI_PWR_UP			0x04
> @@ -265,6 +273,11 @@ enum {
>  };
>  
>  struct dw_mipi_dsi_plat_data {
> +	u32 dsi0_en_bit;
> +	u32 dsi1_en_bit;
> +	u32 grf_switch_reg;
> +	u32 grf_dsi0_mode;
> +	u32 grf_dsi0_mode_reg;
>  	unsigned int max_data_lanes;
>  	enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
>  					   struct drm_display_mode *mode);
> @@ -281,6 +294,7 @@ struct dw_mipi_dsi {
>  
>  	struct clk *pllref_clk;
>  	struct clk *pclk;
> +	struct clk *phy_cfg_clk;
>  
>  	unsigned int lane_mbps; /* per lane */
>  	u32 channel;
> @@ -426,6 +440,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>  	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
>  	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>  
> +	if (dsi->phy_cfg_clk) {

You don't need this check any longer.

> +		ret = clk_prepare_enable(dsi->phy_cfg_clk);
> +		if (ret) {
> +			dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
> +			return ret;
> +		}
> +	}
> +
>  	dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
>  					 VCO_RANGE_CON_SEL(vco) |
>  					 VCO_IN_CAP_CON_LOW |
> @@ -479,17 +501,19 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>  				 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
>  	if (ret < 0) {
>  		dev_err(dsi->dev, "failed to wait for phy lock state\n");
> -		return ret;
> +		goto phy_init_end;
>  	}
>  
>  	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>  				 val, val & STOP_STATE_CLK_LANE, 1000,
>  				 PHY_STATUS_TIMEOUT_US);
> -	if (ret < 0) {
> +	if (ret < 0)
>  		dev_err(dsi->dev,
>  			"failed to wait for phy clk lane stop state\n");
> -		return ret;
> -	}
> +
> +phy_init_end:
> +	if (dsi->phy_cfg_clk)

Or this

> +		clk_disable_unprepare(dsi->phy_cfg_clk);
>  
>  	return ret;
>  }
> @@ -965,6 +989,7 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>  static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>  {
>  	struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
> +	const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
>  	int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
>  	u32 val;
>  
> @@ -985,6 +1010,10 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>  	dw_mipi_dsi_dphy_interface_config(dsi);
>  	dw_mipi_dsi_clear_err(dsi);
>  
> +	if (pdata->grf_dsi0_mode_reg)
> +		regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
> +			     pdata->grf_dsi0_mode);
> +
>  	dw_mipi_dsi_phy_init(dsi);
>  	dw_mipi_dsi_wait_for_two_frames(dsi);
>  
> @@ -998,11 +1027,11 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>  	clk_disable_unprepare(dsi->pclk);
>  
>  	if (mux)
> -		val = DSI0_SEL_VOP_LIT | (DSI0_SEL_VOP_LIT << 16);
> +		val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
>  	else
> -		val = DSI0_SEL_VOP_LIT << 16;
> +		val = pdata->dsi0_en_bit << 16;
>  
> -	regmap_write(dsi->grf_regmap, GRF_SOC_CON6, val);
> +	regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
>  	dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
>  }
>  
> @@ -1162,14 +1191,29 @@ static enum drm_mode_status rk3288_mipi_dsi_mode_valid(
>  }
>  
>  static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
> +	.dsi0_en_bit = RK3288_DSI0_SEL_VOP_LIT,
> +	.dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
> +	.grf_switch_reg = RK3288_GRF_SOC_CON6,
>  	.max_data_lanes = 4,
>  	.mode_valid = rk3288_mipi_dsi_mode_valid,
>  };
>  
> +static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
> +	.dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
> +	.dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
> +	.grf_switch_reg = RK3399_GRF_SOC_CON19,
> +	.grf_dsi0_mode = RK3399_GRF_DSI_MODE,
> +	.grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
> +	.max_data_lanes = 4,
> +};
> +
>  static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
>  	{
>  	 .compatible = "rockchip,rk3288-mipi-dsi",
>  	 .data = &rk3288_mipi_dsi_drv_data,
> +	}, {
> +	 .compatible = "rockchip,rk3399-mipi-dsi",
> +	 .data = &rk3399_mipi_dsi_drv_data,
>  	},
>  	{ /* sentinel */ }
>  };
> @@ -1249,6 +1293,17 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
>  		clk_disable_unprepare(dsi->pclk);
>  	}
>  
> +	dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
> +	if (IS_ERR(dsi->phy_cfg_clk)) {
> +		ret = PTR_ERR(dsi->phy_cfg_clk);
> +		if (ret != -ENOENT) {
> +			dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret);
> +			return ret;
> +		}
> +		dsi->phy_cfg_clk = NULL;
> +		dev_dbg(dev, "have not phy_cfg_clk\n");
> +	}
> +
>  	ret = clk_prepare_enable(dsi->pllref_clk);
>  	if (ret) {
>  		dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
> -- 
> 2.6.3
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Sean Paul, Software Engineer, Google / Chromium OS

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