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| Started by | tip-bot for Grzegorz Andrejczuk <tipbot@zytor.com> |
|---|---|
| First post | 2017-02-04 17:40 +0100 |
| Last post | 2017-02-04 17:40 +0100 |
| Articles | 1 — 1 participant |
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[tip:x86/cpufeature] x86/cpufeature: Add RING3MWAIT to CPU features tip-bot for Grzegorz Andrejczuk <tipbot@zytor.com> - 2017-02-04 17:40 +0100
| From | tip-bot for Grzegorz Andrejczuk <tipbot@zytor.com> |
|---|---|
| Date | 2017-02-04 17:40 +0100 |
| Subject | [tip:x86/cpufeature] x86/cpufeature: Add RING3MWAIT to CPU features |
| Message-ID | <t7bxw-31R-25@gated-at.bofh.it> |
Commit-ID: 1d12d0ef0194ccc4dcebed3d96bb2301b26fc3ee Gitweb: http://git.kernel.org/tip/1d12d0ef0194ccc4dcebed3d96bb2301b26fc3ee Author: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> AuthorDate: Fri, 20 Jan 2017 14:22:35 +0100 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sat, 4 Feb 2017 08:51:09 +0100 x86/cpufeature: Add RING3MWAIT to CPU features Add software-defined CPUID bit for the non-architectural ring 3 MONITOR/MWAIT feature. Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> Cc: Piotr.Luc@intel.com Cc: dave.hansen@linux.intel.com Link: http://lkml.kernel.org/r/1484918557-15481-4-git-send-email-grzegorz.andrejczuk@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/include/asm/cpufeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d9d7136..56e5184 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -100,7 +100,7 @@ #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */ #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ -/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ +#define X86_FEATURE_RING3MWAIT ( 3*32+25) /* ring 3 MONITOR/MWAIT */ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
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