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[tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for Knights Mill

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  [tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for Knights  Mill tip-bot for Piotr Luc <tipbot@zytor.com> - 2017-02-04 17:40 +0100
    RE: [tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for  Knights Mill "Luc, Piotr" <Piotr.Luc@intel.com> - 2017-02-04 22:50 +0100

#1573709 — [tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for Knights Mill

Commit-ID:  2fc70d88d85d55e85bad7fde0ee71f79e22bfa3f
Gitweb:     http://git.kernel.org/tip/2fc70d88d85d55e85bad7fde0ee71f79e22bfa3f
Author:     Piotr Luc <piotr.luc@intel.com>
AuthorDate: Fri, 20 Jan 2017 14:22:37 +0100
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sat, 4 Feb 2017 08:51:10 +0100

x86/cpufeature: Enable RING3MWAIT for Knights Mill

Enable ring 3 MONITOR/MWAIT for Intel Xeon Phi codenamed Knights Mill. We
can't guarantee that this (KNM) will be the last CPU model that needs this
hack.  But, we do recognize that this is far from optimal, and there is an
effort to ensure we don't keep doing extending this hack forever.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Cc: Piotr.Luc@intel.com
Cc: dave.hansen@linux.intel.com
Link: http://lkml.kernel.org/r/1484918557-15481-6-git-send-email-grzegorz.andrejczuk@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 arch/x86/kernel/cpu/intel.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index da2401a..74f30f9 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -79,8 +79,15 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
 	 * Ring 3 MONITOR/MWAIT feature cannot be detected without
 	 * cpu model and family comparison.
 	 */
-	if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+	if (c->x86 != 6)
 		return;
+	switch (c->x86_model) {
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
+		break:
+	default:
+		return;
+	}
 
 	if (ring3mwait_disabled) {
 		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,

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#1573762 — RE: [tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for Knights Mill

Hi Thomas,

It looks like there is a typo with the line with 'break' - it should be semicolon there.
Could you fix it, please?

Thx,
Piotr

> 
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> Cc: Piotr.Luc@intel.com
> Cc: dave.hansen@linux.intel.com
> Link: http://lkml.kernel.org/r/1484918557-15481-6-git-send-email-
> grzegorz.andrejczuk@intel.com
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> 
...
> +	case INTEL_FAM6_XEON_PHI_KNL:
> +	case INTEL_FAM6_XEON_PHI_KNM:
> +		break:
> +	default:
...

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