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| Started by | Mark Rutland <mark.rutland@arm.com> |
|---|---|
| First post | 2017-02-06 17:50 +0100 |
| Last post | 2017-02-06 17:50 +0100 |
| Articles | 1 — 1 participant |
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[PATCH 1/4] arm64: arch_timer: add dt binding for hisilicon-161010101 erratum Mark Rutland <mark.rutland@arm.com> - 2017-02-06 17:50 +0100
| From | Mark Rutland <mark.rutland@arm.com> |
|---|---|
| Date | 2017-02-06 17:50 +0100 |
| Subject | [PATCH 1/4] arm64: arch_timer: add dt binding for hisilicon-161010101 erratum |
| Message-ID | <t7UEi-7p1-19@gated-at.bofh.it> |
From: Ding Tianhong <dingtianhong@huawei.com> This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2..e926aea 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize -- 1.9.1
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