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[PATCH] ARM: dts: Add EMAC AXI settings for Arria10

Started bythor.thayer@linux.intel.com
First post2017-02-02 18:10 +0100
Last post2017-02-02 20:30 +0100
Articles 2 — 2 participants

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  [PATCH] ARM: dts: Add EMAC AXI settings for Arria10 thor.thayer@linux.intel.com - 2017-02-02 18:10 +0100
    Re: [PATCH] ARM: dts: Add EMAC AXI settings for Arria10 Dinh Nguyen <dinh.linux@gmail.com> - 2017-02-02 20:30 +0100

#1572520 — [PATCH] ARM: dts: Add EMAC AXI settings for Arria10

Fromthor.thayer@linux.intel.com
Date2017-02-02 18:10 +0100
Subject[PATCH] ARM: dts: Add EMAC AXI settings for Arria10
Message-ID<t6t3r-6OU-1@gated-at.bofh.it>
From: Thor Thayer <thor.thayer@linux.intel.com>

Add the device tree entries needed to support the EMAC AXI
bus settings on the Arria10 SoCFPGA chip.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index f520cbf..f05dd15 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -400,6 +400,12 @@
 				};
 		};
 
+		socfpga_axi_setup: stmmac-axi-config {
+			snps,wr_osr_lmt = <0xf>;
+			snps,rd_osr_lmt = <0xf>;
+			snps,blen = <0 0 0 0 16 0 0>;
+		};
+
 		gmac0: ethernet@ff800000 {
 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
@@ -416,6 +422,7 @@
 			clock-names = "stmmaceth";
 			resets = <&rst EMAC0_RESET>;
 			reset-names = "stmmaceth";
+			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
 
-- 
2.7.4

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#1572699

FromDinh Nguyen <dinh.linux@gmail.com>
Date2017-02-02 20:30 +0100
Message-ID<t6veW-89s-27@gated-at.bofh.it>
In reply to#1572520
On Thu, Feb 2, 2017 at 11:09 AM,  <thor.thayer@linux.intel.com> wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Add the device tree entries needed to support the EMAC AXI
> bus settings on the Arria10 SoCFPGA chip.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
>  arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index f520cbf..f05dd15 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -400,6 +400,12 @@
>                                 };
>                 };
>
> +               socfpga_axi_setup: stmmac-axi-config {
> +                       snps,wr_osr_lmt = <0xf>;
> +                       snps,rd_osr_lmt = <0xf>;
> +                       snps,blen = <0 0 0 0 16 0 0>;
> +               };
> +
>                 gmac0: ethernet@ff800000 {
>                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
>                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> @@ -416,6 +422,7 @@
>                         clock-names = "stmmaceth";
>                         resets = <&rst EMAC0_RESET>;
>                         reset-names = "stmmaceth";
> +                       snps,axi-config = <&socfpga_axi_setup>;

What about gmac1 and gmac2? They probably need this entry as well.

Dinh

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