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Groups > linux.kernel > #1565442 > unrolled thread
| Started by | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| First post | 2017-01-24 03:40 +0100 |
| Last post | 2017-01-27 22:20 +0100 |
| Articles | 11 — 4 participants |
Back to article view | Back to linux.kernel
[PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai <wens@csie.org> - 2017-01-24 03:40 +0100
[PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag Chen-Yu Tsai <wens@csie.org> - 2017-01-24 03:40 +0100
[PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings Chen-Yu Tsai <wens@csie.org> - 2017-01-24 03:40 +0100
[PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai <wens@csie.org> - 2017-01-24 03:40 +0100
Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-01-26 11:40 +0100
Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai <wens@csie.org> - 2017-01-26 12:30 +0100
Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai <wens@csie.org> - 2017-01-27 10:30 +0100
Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-01-27 10:50 +0100
Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-01-27 21:10 +0100
Re: [linux-sunxi] [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Priit Laes <plaes@plaes.org> - 2017-01-24 07:20 +0100
Re: [PATCH 05/11] clk: sunxi-ng: Add A80 CCU Rob Herring <robh@kernel.org> - 2017-01-27 22:20 +0100
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-01-24 03:40 +0100 |
| Subject | [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs |
| Message-ID | <t2ZbA-6F4-5@gated-at.bofh.it> |
Hi everyone,
This series adds new "sunxi-ng" style drivers for the CCUs found in the
Allwinner A80 SoC. The A80 contains 1 main clock control unit, and some
subsystem specific clock control units at separate addresses. These
include the USB, display engine, and MMC.
- The MMC clocks can be supported by the old clock drivers,
hence here we do not add a new driver for it.
- The old USB clock driver is intertwined with other SoCs,
requires old style bindings with clock-output-names and
CLK_OF_DECLARE for its parents. It is easier to switch
to a new binding and driver.
- The display engine (DE) CCU was not supported in the past.
The A80 CCU also has some quirks about its design. It has
- Separate registers for PLL lock status
- P1, P2 dividers, which are power-of-2 and only 1 bit wide
The first 3 patches fix and extend the behavior of sunxi-ng's
mux clock type, based on the behavior of the clk subsystem's
basic mux clock.
The fourth patch adds support for checking PLL lock status
bits in separate registers, as opposed to within the PLL's
config register.
Patches 5 through 7 add drivers for the CCU blocks.
Patches 8 through 10 do some cleanup of the sunxi/allwinner dts
files prior to switching sun9i dts to the new sunxi-ng clock
bindings. These are independent of the clk stuff, but touch the
same lines for sun9i. Including them should make it easier to
apply and test patches.
Patch 11 has sun9i switch over to the new clock bindings.
Please take a look and let me know what you think.
I also have a series adding support for the first display pipeline
of the A80 with RGB LCD panel output which I will send out later
on.
Regards
ChenYu
Chen-Yu Tsai (11):
clk: sunxi-ng: mux: Fix determine_rate for mux clocks with
pre-dividers
clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
clk: sunxi-ng: mux: Get closest parent rate possible with
CLK_SET_RATE_PARENT
clk: sunxi-ng: Support separately grouped PLL lock status register
clk: sunxi-ng: Add A80 CCU
clk: sunxi-ng: Add A80 USB CCU
clk: sunxi-ng: Add A80 Display Engine CCU
ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio
ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header
arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h
header
ARM: dts: sun9i: Switch to new clock bindings
.../devicetree/bindings/clock/sun9i-de.txt | 28 +
.../devicetree/bindings/clock/sun9i-usb.txt | 24 +
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
arch/arm/boot/dts/sun4i-a10-a1000.dts | 1 -
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 -
arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 1 -
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 1 -
arch/arm/boot/dts/sun4i-a10-inet1.dts | 1 -
arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 1 -
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 1 -
arch/arm/boot/dts/sun4i-a10-marsboard.dts | 1 -
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 1 -
arch/arm/boot/dts/sun4i-a10-mk802.dts | 1 -
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 1 -
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 1 -
arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 1 -
arch/arm/boot/dts/sun4i-a10.dtsi | 1 -
arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 1 -
arch/arm/boot/dts/sun5i-a10s.dtsi | 1 -
.../boot/dts/sun5i-a13-empire-electronix-d709.dts | 1 -
arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 1 -
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 1 -
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 1 -
arch/arm/boot/dts/sun5i-a13.dtsi | 1 -
arch/arm/boot/dts/sun5i-gr8.dtsi | 1 -
arch/arm/boot/dts/sun5i.dtsi | 1 -
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 1 -
arch/arm/boot/dts/sun6i-a31-colombus.dts | 1 -
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 1 -
arch/arm/boot/dts/sun6i-a31-i7.dts | 1 -
arch/arm/boot/dts/sun6i-a31-m9.dts | 1 -
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 1 -
arch/arm/boot/dts/sun6i-a31.dtsi | 1 -
arch/arm/boot/dts/sun6i-a31s-cs908.dts | 2 -
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 1 -
arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 1 -
.../dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 1 -
.../boot/dts/sun6i-reference-design-tablet.dtsi | 1 -
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 1 -
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 -
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 -
arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 1 -
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 1 -
arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 1 -
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 1 -
arch/arm/boot/dts/sun7i-a20-m3.dts | 1 -
arch/arm/boot/dts/sun7i-a20-mk808c.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 1 -
arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 1 -
arch/arm/boot/dts/sun7i-a20-orangepi.dts | 1 -
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 1 -
arch/arm/boot/dts/sun7i-a20.dtsi | 1 -
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 -
arch/arm/boot/dts/sun8i-a23-evb.dts | 1 -
arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 10 -
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 1 -
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 -
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 1 -
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 1 -
arch/arm/boot/dts/sun8i-h3.dtsi | 1 -
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 1 -
arch/arm/boot/dts/sun9i-a80-optimus.dts | 1 -
arch/arm/boot/dts/sun9i-a80.dtsi | 404 ++-----
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 1 -
.../boot/dts/sunxi-reference-design-tablet.dtsi | 1 -
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 -
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 3 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 +
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 1223 ++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun9i-a80.h | 57 +
drivers/clk/sunxi-ng/ccu_common.c | 8 +-
drivers/clk/sunxi-ng/ccu_common.h | 2 +
drivers/clk/sunxi-ng/ccu_mux.c | 35 +-
include/dt-bindings/clock/sun9i-a80-ccu.h | 162 +++
.../dt-bindings/clock/sun9i-a80-de.h | 73 +-
.../dt-bindings/clock/sun9i-a80-usb.h | 44 +-
.../dt-bindings/reset/sun9i-a80-ccu.h | 91 +-
.../dt-bindings/reset/sun9i-a80-de.h | 45 +-
.../dt-bindings/reset/sun9i-a80-usb.h | 41 +-
94 files changed, 2270 insertions(+), 550 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.h
create mode 100644 include/dt-bindings/clock/sun9i-a80-ccu.h
copy arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi => include/dt-bindings/clock/sun9i-a80-de.h (67%)
copy arch/arm/boot/dts/sun8i-a23-q8-tablet.dts => include/dt-bindings/clock/sun9i-a80-usb.h (73%)
copy arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi => include/dt-bindings/reset/sun9i-a80-ccu.h (56%)
copy arch/arm/boot/dts/sun8i-a23-q8-tablet.dts => include/dt-bindings/reset/sun9i-a80-de.h (73%)
copy arch/arm/boot/dts/sun8i-a23-q8-tablet.dts => include/dt-bindings/reset/sun9i-a80-usb.h (73%)
--
2.11.0
[toc] | [next] | [standalone]
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-01-24 03:40 +0100 |
| Subject | [PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag |
| Message-ID | <t2ZbB-6F4-43@gated-at.bofh.it> |
| In reply to | #1565442 |
This patch adds support for the CLK_SET_RATE_NO_REPARENT flag to the
mux determine_rate helper, based on examples from clk-composite and
clk-mux.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi-ng/ccu_mux.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 3445041894e7..7cee17cf9c19 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -70,6 +70,21 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
struct clk_hw *best_parent, *hw = &common->hw;
unsigned int i;
+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
+ unsigned long adj_parent_rate;
+
+ best_parent = clk_hw_get_parent(hw);
+ best_parent_rate = clk_hw_get_rate(best_parent);
+
+ adj_parent_rate = best_parent_rate;
+ ccu_mux_helper_adjust_parent_for_prediv(common, cm, -1,
+ &adj_parent_rate);
+
+ best_rate = round(cm, adj_parent_rate, req->rate, data);
+
+ goto out;
+ }
+
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
unsigned long tmp_rate, parent_rate, adj_parent_rate;
struct clk_hw *parent;
--
2.11.0
[toc] | [prev] | [next] | [standalone]
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-01-24 03:40 +0100 |
| Subject | [PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings |
| Message-ID | <t2ZbB-6F4-39@gated-at.bofh.it> |
| In reply to | #1565442 |
Now that we have a full clock driver for sun9i, switch to it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 404 +++++++++++----------------------------
1 file changed, 107 insertions(+), 297 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 18b35fc23f46..b763c61cacba 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -46,6 +46,13 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun9i-a80-ccu.h>
+#include <dt-bindings/clock/sun9i-a80-de.h>
+#include <dt-bindings/clock/sun9i-a80-usb.h>
+#include <dt-bindings/reset/sun9i-a80-ccu.h>
+#include <dt-bindings/reset/sun9i-a80-de.h>
+#include <dt-bindings/reset/sun9i-a80-usb.h>
+
/ {
interrupt-parent = <&gic>;
@@ -157,228 +164,13 @@
clock-output-names = "osc32k";
};
- usb_mod_clk: clk@00a08000 {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun9i-a80-usb-mod-clk";
- reg = <0x00a08000 0x4>;
- clocks = <&ahb1_gates 1>;
- clock-output-names = "usb0_ahb", "usb_ohci0",
- "usb1_ahb", "usb_ohci1",
- "usb2_ahb", "usb_ohci2";
- };
-
- usb_phy_clk: clk@00a08004 {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "allwinner,sun9i-a80-usb-phy-clk";
- reg = <0x00a08004 0x4>;
- clocks = <&ahb1_gates 1>;
- clock-output-names = "usb_phy0", "usb_hsic1_480M",
- "usb_phy1", "usb_hsic2_480M",
- "usb_phy2", "usb_hsic_12M";
- };
-
- pll3: clk@06000008 {
- /* placeholder until implemented */
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-rate = <0>;
- clock-output-names = "pll3";
- };
-
- pll4: clk@0600000c {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-pll4-clk";
- reg = <0x0600000c 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll4";
- };
-
- pll12: clk@0600002c {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-pll4-clk";
- reg = <0x0600002c 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll12";
- };
-
- gt_clk: clk@0600005c {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-gt-clk";
- reg = <0x0600005c 0x4>;
- clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "gt";
- };
-
- ahb0: clk@06000060 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-ahb-clk";
- reg = <0x06000060 0x4>;
- clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "ahb0";
- };
-
- ahb1: clk@06000064 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-ahb-clk";
- reg = <0x06000064 0x4>;
- clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "ahb1";
- };
-
- ahb2: clk@06000068 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-ahb-clk";
- reg = <0x06000068 0x4>;
- clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "ahb2";
- };
-
- apb0: clk@06000070 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-apb0-clk";
- reg = <0x06000070 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "apb0";
- };
-
- apb1: clk@06000074 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-apb1-clk";
- reg = <0x06000074 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "apb1";
- };
-
- cci400_clk: clk@06000078 {
- #clock-cells = <0>;
- compatible = "allwinner,sun9i-a80-gt-clk";
- reg = <0x06000078 0x4>;
- clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
- clock-output-names = "cci400";
- };
-
- mmc0_clk: clk@06000410 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x06000410 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc0", "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@06000414 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x06000414 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc1", "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@06000418 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x06000418 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc2", "mmc2_output",
- "mmc2_sample";
- };
-
- mmc3_clk: clk@0600041c {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-mmc-clk";
- reg = <0x0600041c 0x4>;
- clocks = <&osc24M>, <&pll4>;
- clock-output-names = "mmc3", "mmc3_output",
- "mmc3_sample";
- };
-
- ahb0_gates: clk@06000580 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
- reg = <0x06000580 0x4>;
- clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>,
- <5>, <8>, <12>,
- <13>, <14>,
- <15>, <16>, <18>,
- <20>, <21>, <22>,
- <23>;
- clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
- "ahb0_ss", "ahb0_sd", "ahb0_nand1",
- "ahb0_nand0", "ahb0_sdram",
- "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
- "ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
- "ahb0_spi3";
- };
-
- ahb1_gates: clk@06000584 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
- reg = <0x06000584 0x4>;
- clocks = <&ahb1>;
- clock-indices = <0>, <1>,
- <17>, <21>,
- <22>, <23>,
- <24>;
- clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
- "ahb1_gmac", "ahb1_msgbox",
- "ahb1_spinlock", "ahb1_hstimer",
- "ahb1_dma";
- };
-
- ahb2_gates: clk@06000588 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
- reg = <0x06000588 0x4>;
- clocks = <&ahb2>;
- clock-indices = <0>, <1>,
- <2>, <4>, <5>,
- <7>, <8>, <11>;
- clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
- "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
- "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
- };
-
- apb0_gates: clk@06000590 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-apb0-gates-clk";
- reg = <0x06000590 0x4>;
- clocks = <&apb0>;
- clock-indices = <1>, <5>,
- <11>, <12>, <13>,
- <15>, <17>, <18>,
- <19>;
- clock-output-names = "apb0_spdif", "apb0_pio",
- "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
- "apb0_lradc", "apb0_gpadc", "apb0_twd",
- "apb0_cirtx";
- };
-
- apb1_gates: clk@06000594 {
- #clock-cells = <1>;
- compatible = "allwinner,sun9i-a80-apb1-gates-clk";
- reg = <0x06000594 0x4>;
- clocks = <&apb1>;
- clock-indices = <0>, <1>,
- <2>, <3>, <4>,
- <16>, <17>,
- <18>, <19>,
- <20>, <21>;
- clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
- "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5";
- };
-
cpus_clk: clk@08001410 {
compatible = "allwinner,sun9i-a80-cpus-clk";
reg = <0x08001410 0x4>;
#clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
+ clocks = <&osc32k>, <&osc24M>,
+ <&ccu CLK_PLL_PERIPH0>,
+ <&ccu CLK_PLL_AUDIO>;
clock-output-names = "cpus";
};
@@ -451,8 +243,8 @@
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 1>;
- resets = <&usb_mod_clk 17>;
+ clocks = <&usb_clocks CLK_BUS_HCI0>;
+ resets = <&usb_clocks RST_USB0_HCI>;
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
@@ -462,8 +254,9 @@
compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
reg = <0x00a00400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
- resets = <&usb_mod_clk 17>;
+ clocks = <&usb_clocks CLK_BUS_HCI0>,
+ <&usb_clocks CLK_USB_OHCI0>;
+ resets = <&usb_clocks RST_USB0_HCI>;
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
@@ -472,9 +265,9 @@
usbphy1: phy@00a00800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a00800 0x4>;
- clocks = <&usb_phy_clk 1>;
+ clocks = <&usb_clocks CLK_USB0_PHY>;
clock-names = "phy";
- resets = <&usb_phy_clk 17>;
+ resets = <&usb_clocks RST_USB0_PHY>;
reset-names = "phy";
status = "disabled";
#phy-cells = <0>;
@@ -484,8 +277,8 @@
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a01000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 3>;
- resets = <&usb_mod_clk 18>;
+ clocks = <&usb_clocks CLK_BUS_HCI1>;
+ resets = <&usb_clocks RST_USB1_HCI>;
phys = <&usbphy2>;
phy-names = "usb";
status = "disabled";
@@ -494,11 +287,16 @@
usbphy2: phy@00a01800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>;
- clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
- <&usb_phy_clk 3>;
- clock-names = "hsic_480M", "hsic_12M", "phy";
- resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
- reset-names = "hsic", "phy";
+ clocks = <&usb_clocks CLK_USB1_HSIC>,
+ <&usb_clocks CLK_USB_HSIC>,
+ <&usb_clocks CLK_USB1_PHY>;
+ clock-names = "hsic_480M",
+ "hsic_12M",
+ "phy";
+ resets = <&usb_clocks RST_USB1_HSIC>,
+ <&usb_clocks RST_USB1_PHY>;
+ reset-names = "hsic",
+ "phy";
status = "disabled";
#phy-cells = <0>;
/* usb1 is always used with HSIC */
@@ -509,8 +307,8 @@
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a02000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 5>;
- resets = <&usb_mod_clk 19>;
+ clocks = <&usb_clocks CLK_BUS_HCI2>;
+ resets = <&usb_clocks RST_USB2_HCI>;
phys = <&usbphy3>;
phy-names = "usb";
status = "disabled";
@@ -520,8 +318,9 @@
compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
reg = <0x00a02400 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
- resets = <&usb_mod_clk 19>;
+ clocks = <&usb_clocks CLK_BUS_HCI2>,
+ <&usb_clocks CLK_USB_OHCI2>;
+ resets = <&usb_clocks RST_USB2_HCI>;
phys = <&usbphy3>;
phy-names = "usb";
status = "disabled";
@@ -530,20 +329,35 @@
usbphy3: phy@00a02800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a02800 0x4>;
- clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
- <&usb_phy_clk 5>;
- clock-names = "hsic_480M", "hsic_12M", "phy";
- resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
- reset-names = "hsic", "phy";
+ clocks = <&usb_clocks CLK_USB2_HSIC>,
+ <&usb_clocks CLK_USB_HSIC>,
+ <&usb_clocks CLK_USB2_PHY>;
+ clock-names = "hsic_480M",
+ "hsic_12M",
+ "phy";
+ resets = <&usb_clocks RST_USB2_HSIC>,
+ <&usb_clocks RST_USB2_PHY>;
+ reset-names = "hsic",
+ "phy";
status = "disabled";
#phy-cells = <0>;
};
+ usb_clocks: clock@00a08000 {
+ compatible = "allwinner,sun9i-a80-usb-clks";
+ reg = <0x00a08000 0x8>;
+ clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
+ clock-names = "bus", "hosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
- <&mmc0_clk 1>, <&mmc0_clk 2>;
+ clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 0>;
reset-names = "ahb";
@@ -556,8 +370,9 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
- <&mmc1_clk 1>, <&mmc1_clk 2>;
+ clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 1>;
reset-names = "ahb";
@@ -570,8 +385,9 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
- <&mmc2_clk 1>, <&mmc2_clk 2>;
+ clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 2>;
reset-names = "ahb";
@@ -584,8 +400,9 @@
mmc3: mmc@01c12000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
- <&mmc3_clk 1>, <&mmc3_clk 2>;
+ clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
+ <&ccu CLK_MMC3_OUTPUT>,
+ <&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 3>;
reset-names = "ahb";
@@ -598,9 +415,9 @@
mmc_config_clk: clk@01c13000 {
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
- clocks = <&ahb0_gates 8>;
+ clocks = <&ccu CLK_BUS_MMC>;
clock-names = "ahb";
- resets = <&ahb0_resets 8>;
+ resets = <&ccu RST_BUS_MMC>;
reset-names = "ahb";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -619,34 +436,27 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- ahb0_resets: reset@060005a0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005a0 0x4>;
- };
-
- ahb1_resets: reset@060005a4 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005a4 0x4>;
- };
-
- ahb2_resets: reset@060005a8 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005a8 0x4>;
- };
-
- apb0_resets: reset@060005b0 {
+ de_clocks: clock@03000000 {
+ compatible = "allwinner,sun9i-a80-de-clks";
+ reg = <0x03000000 0x30>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_SDRAM>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "dram",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
#reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005b0 0x4>;
};
- apb1_resets: reset@060005b4 {
+ ccu: clock@06000000 {
+ compatible = "allwinner,sun9i-a80-ccu";
+ reg = <0x06000000 0x800>;
+ clocks = <&osc24M>, <&osc32k>;
+ clock-names = "hosc", "losc";
+ #clock-cells = <1>;
#reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x060005b4 0x4>;
};
timer@06000c00 {
@@ -676,7 +486,7 @@
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -732,8 +542,8 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 16>;
- resets = <&apb1_resets 16>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -743,8 +553,8 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 17>;
- resets = <&apb1_resets 17>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -754,8 +564,8 @@
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 18>;
- resets = <&apb1_resets 18>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
@@ -765,8 +575,8 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 19>;
- resets = <&apb1_resets 19>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
@@ -776,8 +586,8 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 20>;
- resets = <&apb1_resets 20>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
@@ -787,8 +597,8 @@
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&apb1_gates 21>;
- resets = <&apb1_resets 21>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
status = "disabled";
};
@@ -796,8 +606,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002800 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 0>;
- resets = <&apb1_resets 0>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -807,8 +617,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002c00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 1>;
- resets = <&apb1_resets 1>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -818,8 +628,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 2>;
- resets = <&apb1_resets 2>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -829,8 +639,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003400 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 3>;
- resets = <&apb1_resets 3>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -840,8 +650,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003800 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 4>;
- resets = <&apb1_resets 4>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0
[toc] | [prev] | [next] | [standalone]
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-01-24 03:40 +0100 |
| Subject | [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU |
| Message-ID | <t2ZbB-6F4-49@gated-at.bofh.it> |
| In reply to | #1565442 |
Add support for the display engine clock controls found on the A80.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
.../devicetree/bindings/clock/sun9i-de.txt | 28 ++
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++
include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++
include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++
6 files changed, 483 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h
create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h
diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
new file mode 100644
index 000000000000..3a5e6df70677
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
@@ -0,0 +1,28 @@
+Allwinner A80 Display Engine Clock Control Binding
+------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+ - "allwinner,sun9i-a80-de-clocks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+ - "mod": the display engine module clock
+ - "dram": the DRAM bus clock for the system
+ - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de_clocks: clock@03000000 {
+ compatible = "allwinner,sun9i-a80-de-clks";
+ reg = <0x03000000 0x30>;
+ clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
+ clock-names = "mod", "dram", "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 8f37ef7fb67d..6feaac0c5600 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
+obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
new file mode 100644
index 000000000000..3fc27db0a49a
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "ccu_common.h"
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_reset.h"
+
+#include "ccu-sun9i-a80-de.h"
+
+static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
+ 0x00, BIT(0), 0);
+static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
+ 0x00, BIT(1), 0);
+static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
+ 0x00, BIT(2), 0);
+static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
+ 0x00, BIT(4), 0);
+static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
+ 0x00, BIT(5), 0);
+static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
+ 0x00, BIT(8), 0);
+static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
+ 0x00, BIT(9), 0);
+static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
+ 0x00, BIT(10), 0);
+static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
+ 0x00, BIT(12), 0);
+static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
+ 0x00, BIT(13), 0);
+static SUNXI_CCU_GATE(merge_clk, "merge", "de",
+ 0x00, BIT(20), 0);
+
+static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
+ 0x04, BIT(0), 0);
+static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
+ 0x04, BIT(1), 0);
+static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
+ 0x04, BIT(2), 0);
+static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
+ 0x04, BIT(4), 0);
+static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
+ 0x04, BIT(5), 0);
+static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
+ 0x04, BIT(8), 0);
+static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
+ 0x04, BIT(9), 0);
+static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
+ 0x04, BIT(10), 0);
+static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
+ 0x04, BIT(12), 0);
+static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
+ 0x04, BIT(13), 0);
+
+static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
+ 0x08, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
+ 0x08, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
+ 0x08, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
+ 0x08, BIT(4), 0);
+static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
+ 0x08, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
+ 0x08, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
+ 0x08, BIT(9), 0);
+static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
+ 0x08, BIT(10), 0);
+static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
+ 0x08, BIT(12), 0);
+static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
+ 0x08, BIT(13), 0);
+
+static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
+static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
+static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
+static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
+static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
+static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
+
+static struct ccu_common *sun9i_a80_de_clks[] = {
+ &fe0_clk.common,
+ &fe1_clk.common,
+ &fe2_clk.common,
+ &iep_deu0_clk.common,
+ &iep_deu1_clk.common,
+ &be0_clk.common,
+ &be1_clk.common,
+ &be2_clk.common,
+ &iep_drc0_clk.common,
+ &iep_drc1_clk.common,
+ &merge_clk.common,
+
+ &dram_fe0_clk.common,
+ &dram_fe1_clk.common,
+ &dram_fe2_clk.common,
+ &dram_deu0_clk.common,
+ &dram_deu1_clk.common,
+ &dram_be0_clk.common,
+ &dram_be1_clk.common,
+ &dram_be2_clk.common,
+ &dram_drc0_clk.common,
+ &dram_drc1_clk.common,
+
+ &bus_fe0_clk.common,
+ &bus_fe1_clk.common,
+ &bus_fe2_clk.common,
+ &bus_deu0_clk.common,
+ &bus_deu1_clk.common,
+ &bus_be0_clk.common,
+ &bus_be1_clk.common,
+ &bus_be2_clk.common,
+ &bus_drc0_clk.common,
+ &bus_drc1_clk.common,
+
+ &fe0_div_clk.common,
+ &fe1_div_clk.common,
+ &fe2_div_clk.common,
+ &be0_div_clk.common,
+ &be1_div_clk.common,
+ &be2_div_clk.common,
+};
+
+static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = {
+ .hws = {
+ [CLK_FE0] = &fe0_clk.common.hw,
+ [CLK_FE1] = &fe1_clk.common.hw,
+ [CLK_FE2] = &fe2_clk.common.hw,
+ [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
+ [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
+ [CLK_BE0] = &be0_clk.common.hw,
+ [CLK_BE1] = &be1_clk.common.hw,
+ [CLK_BE2] = &be2_clk.common.hw,
+ [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
+ [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
+ [CLK_MERGE] = &merge_clk.common.hw,
+
+ [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
+ [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
+ [CLK_DRAM_FE2] = &dram_fe2_clk.common.hw,
+ [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
+ [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
+ [CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
+ [CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
+ [CLK_DRAM_BE2] = &dram_be2_clk.common.hw,
+ [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
+ [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
+
+ [CLK_BUS_FE0] = &bus_fe0_clk.common.hw,
+ [CLK_BUS_FE1] = &bus_fe1_clk.common.hw,
+ [CLK_BUS_FE2] = &bus_fe2_clk.common.hw,
+ [CLK_BUS_DEU0] = &bus_deu0_clk.common.hw,
+ [CLK_BUS_DEU1] = &bus_deu1_clk.common.hw,
+ [CLK_BUS_BE0] = &bus_be0_clk.common.hw,
+ [CLK_BUS_BE1] = &bus_be1_clk.common.hw,
+ [CLK_BUS_BE2] = &bus_be2_clk.common.hw,
+ [CLK_BUS_DRC0] = &bus_drc0_clk.common.hw,
+ [CLK_BUS_DRC1] = &bus_drc1_clk.common.hw,
+
+ [CLK_FE0_DIV] = &fe0_div_clk.common.hw,
+ [CLK_FE1_DIV] = &fe1_div_clk.common.hw,
+ [CLK_FE2_DIV] = &fe2_div_clk.common.hw,
+ [CLK_BE0_DIV] = &be0_div_clk.common.hw,
+ [CLK_BE1_DIV] = &be1_div_clk.common.hw,
+ [CLK_BE2_DIV] = &be2_div_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun9i_a80_de_resets[] = {
+ [RST_FE0] = { 0x0c, BIT(0) },
+ [RST_FE1] = { 0x0c, BIT(1) },
+ [RST_FE2] = { 0x0c, BIT(2) },
+ [RST_DEU0] = { 0x0c, BIT(4) },
+ [RST_DEU1] = { 0x0c, BIT(5) },
+ [RST_BE0] = { 0x0c, BIT(8) },
+ [RST_BE1] = { 0x0c, BIT(9) },
+ [RST_BE2] = { 0x0c, BIT(10) },
+ [RST_DRC0] = { 0x0c, BIT(12) },
+ [RST_DRC1] = { 0x0c, BIT(13) },
+ [RST_MERGE] = { 0x0c, BIT(20) },
+};
+
+static const struct sunxi_ccu_desc sun9i_a80_de_clk_desc = {
+ .ccu_clks = sun9i_a80_de_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun9i_a80_de_clks),
+
+ .hw_clks = &sun9i_a80_de_hw_clks,
+
+ .resets = sun9i_a80_de_resets,
+ .num_resets = ARRAY_SIZE(sun9i_a80_de_resets),
+};
+
+static int sun9i_a80_de_clk_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct clk *bus_clk;
+ struct reset_control *rstc;
+ void __iomem *reg;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg))
+ return PTR_ERR(reg);
+
+ bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(bus_clk)) {
+ ret = PTR_ERR(bus_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret);
+ return ret;
+ }
+
+ rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rstc)) {
+ ret = PTR_ERR(bus_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev,
+ "Couldn't get reset control: %d\n", ret);
+ return ret;
+ }
+
+ /* The bus clock needs to be enabled for us to access the registers */
+ ret = clk_prepare_enable(bus_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
+ return ret;
+ }
+
+ /* The reset control needs to be asserted for the controls to work */
+ ret = reset_control_deassert(rstc);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Couldn't deassert reset control: %d\n", ret);
+ goto err_disable_clk;
+ }
+
+ ret = sunxi_ccu_probe(pdev->dev.of_node, reg,
+ &sun9i_a80_de_clk_desc);
+ if (ret)
+ goto err_assert_reset;
+
+ return 0;
+
+err_assert_reset:
+ reset_control_assert(rstc);
+err_disable_clk:
+ clk_disable_unprepare(bus_clk);
+ return ret;
+}
+
+static const struct of_device_id sun9i_a80_de_clk_ids[] = {
+ { .compatible = "allwinner,sun9i-a80-de-clks" },
+ { }
+};
+
+static struct platform_driver sun9i_a80_de_clk_driver = {
+ .probe = sun9i_a80_de_clk_probe,
+ .driver = {
+ .name = "sun9i-a80-de-clks",
+ .of_match_table = sun9i_a80_de_clk_ids,
+ },
+};
+builtin_platform_driver(sun9i_a80_de_clk_driver);
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
new file mode 100644
index 000000000000..a4769041e40f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN9I_A80_DE_H_
+#define _CCU_SUN9I_A80_DE_H_
+
+#include <dt-bindings/clock/sun9i-a80-de.h>
+#include <dt-bindings/reset/sun9i-a80-de.h>
+
+/* Intermediary clock dividers are not exported */
+#define CLK_FE0_DIV 31
+#define CLK_FE1_DIV 32
+#define CLK_FE2_DIV 33
+#define CLK_BE0_DIV 34
+#define CLK_BE1_DIV 35
+#define CLK_BE2_DIV 36
+
+#define CLK_NUMBER (CLK_BE2_DIV + 1)
+
+#endif /* _CCU_SUN9I_A80_DE_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h
new file mode 100644
index 000000000000..3dad6c3cd131
--- /dev/null
+++ b/include/dt-bindings/clock/sun9i-a80-de.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
+
+#define CLK_FE0 0
+#define CLK_FE1 1
+#define CLK_FE2 2
+#define CLK_IEP_DEU0 3
+#define CLK_IEP_DEU1 4
+#define CLK_BE0 5
+#define CLK_BE1 6
+#define CLK_BE2 7
+#define CLK_IEP_DRC0 8
+#define CLK_IEP_DRC1 9
+#define CLK_MERGE 10
+
+#define CLK_DRAM_FE0 11
+#define CLK_DRAM_FE1 12
+#define CLK_DRAM_FE2 13
+#define CLK_DRAM_DEU0 14
+#define CLK_DRAM_DEU1 15
+#define CLK_DRAM_BE0 16
+#define CLK_DRAM_BE1 17
+#define CLK_DRAM_BE2 18
+#define CLK_DRAM_DRC0 19
+#define CLK_DRAM_DRC1 20
+
+#define CLK_BUS_FE0 21
+#define CLK_BUS_FE1 22
+#define CLK_BUS_FE2 23
+#define CLK_BUS_DEU0 24
+#define CLK_BUS_DEU1 25
+#define CLK_BUS_BE0 26
+#define CLK_BUS_BE1 27
+#define CLK_BUS_BE2 28
+#define CLK_BUS_DRC0 29
+#define CLK_BUS_DRC1 30
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-de.h b/include/dt-bindings/reset/sun9i-a80-de.h
new file mode 100644
index 000000000000..205072770171
--- /dev/null
+++ b/include/dt-bindings/reset/sun9i-a80-de.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
+#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
+
+#define RST_FE0 0
+#define RST_FE1 1
+#define RST_FE2 2
+#define RST_DEU0 3
+#define RST_DEU1 4
+#define RST_BE0 5
+#define RST_BE1 6
+#define RST_BE2 7
+#define RST_DRC0 8
+#define RST_DRC1 9
+#define RST_MERGE 10
+
+#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */
--
2.11.0
[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-01-26 11:40 +0100 |
| Subject | Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU |
| Message-ID | <t3PDc-6bY-1@gated-at.bofh.it> |
| In reply to | #1565449 |
[Multipart message — attachments visible in raw view] — view raw
Hi,
On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote:
> Add support for the display engine clock controls found on the A80.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++
> drivers/clk/sunxi-ng/Makefile | 1 +
> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++
> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++
> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++
> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++
> 6 files changed, 483 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h
> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h
>
> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
> new file mode 100644
> index 000000000000..3a5e6df70677
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
> @@ -0,0 +1,28 @@
> +Allwinner A80 Display Engine Clock Control Binding
> +------------------------------------
> +
> +Required properties :
> +- compatible: must contain one of the following compatibles:
> + - "allwinner,sun9i-a80-de-clocks"
> +
> +- reg: Must contain the registers base address and length
> +- clocks: phandle to the clocks feeding the display engine subsystem.
> + Three are needed:
> + - "mod": the display engine module clock
> + - "dram": the DRAM bus clock for the system
> + - "bus": the bus clock for the whole display engine subsystem
> +- clock-names: Must contain the clock names described just above
> +- resets: phandle to the reset control for the display engine subsystem.
> +- #clock-cells : must contain 1
> +- #reset-cells : must contain 1
> +
> +Example:
> +de_clocks: clock@03000000 {
> + compatible = "allwinner,sun9i-a80-de-clks";
> + reg = <0x03000000 0x30>;
> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
> + clock-names = "mod", "dram", "bus";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +};
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 8f37ef7fb67d..6feaac0c5600 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> new file mode 100644
> index 000000000000..3fc27db0a49a
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> @@ -0,0 +1,283 @@
> +/*
> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu-sun9i-a80-de.h"
> +
> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
> + 0x00, BIT(0), 0);
> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
> + 0x00, BIT(1), 0);
> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
> + 0x00, BIT(2), 0);
> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
> + 0x00, BIT(4), 0);
> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
> + 0x00, BIT(5), 0);
> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
> + 0x00, BIT(8), 0);
> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
> + 0x00, BIT(9), 0);
> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
> + 0x00, BIT(10), 0);
> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
> + 0x00, BIT(12), 0);
> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
> + 0x00, BIT(13), 0);
> +static SUNXI_CCU_GATE(merge_clk, "merge", "de",
> + 0x00, BIT(20), 0);
> +
> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
> + 0x04, BIT(0), 0);
> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
> + 0x04, BIT(1), 0);
> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
> + 0x04, BIT(2), 0);
> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
> + 0x04, BIT(4), 0);
> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
> + 0x04, BIT(5), 0);
> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
> + 0x04, BIT(8), 0);
> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
> + 0x04, BIT(9), 0);
> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
> + 0x04, BIT(10), 0);
> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
> + 0x04, BIT(12), 0);
> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
> + 0x04, BIT(13), 0);
> +
> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
> + 0x08, BIT(0), 0);
> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
> + 0x08, BIT(1), 0);
> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
> + 0x08, BIT(2), 0);
> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
> + 0x08, BIT(4), 0);
> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
> + 0x08, BIT(5), 0);
> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
> + 0x08, BIT(8), 0);
> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
> + 0x08, BIT(9), 0);
> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
> + 0x08, BIT(10), 0);
> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
> + 0x08, BIT(12), 0);
> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
> + 0x08, BIT(13), 0);
> +
> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
I couldn't find any documentation for this CCU.
What are those clocks for, and how the display engine should be using
(ie, which one is it expecting to drive / ungate / etc.)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[toc] | [prev] | [next] | [standalone]
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-01-26 12:30 +0100 |
| Subject | Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU |
| Message-ID | <t3QpA-6Hl-21@gated-at.bofh.it> |
| In reply to | #1567307 |
On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote:
>> Add support for the display engine clock controls found on the A80.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++
>> drivers/clk/sunxi-ng/Makefile | 1 +
>> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++
>> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++
>> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++
>> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++
>> 6 files changed, 483 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
>> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h
>> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
>> new file mode 100644
>> index 000000000000..3a5e6df70677
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
>> @@ -0,0 +1,28 @@
>> +Allwinner A80 Display Engine Clock Control Binding
>> +------------------------------------
>> +
>> +Required properties :
>> +- compatible: must contain one of the following compatibles:
>> + - "allwinner,sun9i-a80-de-clocks"
>> +
>> +- reg: Must contain the registers base address and length
>> +- clocks: phandle to the clocks feeding the display engine subsystem.
>> + Three are needed:
>> + - "mod": the display engine module clock
>> + - "dram": the DRAM bus clock for the system
>> + - "bus": the bus clock for the whole display engine subsystem
>> +- clock-names: Must contain the clock names described just above
>> +- resets: phandle to the reset control for the display engine subsystem.
>> +- #clock-cells : must contain 1
>> +- #reset-cells : must contain 1
>> +
>> +Example:
>> +de_clocks: clock@03000000 {
>> + compatible = "allwinner,sun9i-a80-de-clks";
>> + reg = <0x03000000 0x30>;
>> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
>> + clock-names = "mod", "dram", "bus";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> +};
>> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
>> index 8f37ef7fb67d..6feaac0c5600 100644
>> --- a/drivers/clk/sunxi-ng/Makefile
>> +++ b/drivers/clk/sunxi-ng/Makefile
>> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
>> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
>> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
>> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
>> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
>> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
>> new file mode 100644
>> index 000000000000..3fc27db0a49a
>> --- /dev/null
>> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
>> @@ -0,0 +1,283 @@
>> +/*
>> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_address.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset.h>
>> +
>> +#include "ccu_common.h"
>> +#include "ccu_div.h"
>> +#include "ccu_gate.h"
>> +#include "ccu_reset.h"
>> +
>> +#include "ccu-sun9i-a80-de.h"
>> +
>> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
>> + 0x00, BIT(0), 0);
>> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
>> + 0x00, BIT(1), 0);
>> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
>> + 0x00, BIT(2), 0);
>> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
>> + 0x00, BIT(4), 0);
>> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
>> + 0x00, BIT(5), 0);
>> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
>> + 0x00, BIT(8), 0);
>> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
>> + 0x00, BIT(9), 0);
>> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
>> + 0x00, BIT(10), 0);
>> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
>> + 0x00, BIT(12), 0);
>> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
>> + 0x00, BIT(13), 0);
>> +static SUNXI_CCU_GATE(merge_clk, "merge", "de",
>> + 0x00, BIT(20), 0);
>> +
>> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
>> + 0x04, BIT(0), 0);
>> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
>> + 0x04, BIT(1), 0);
>> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
>> + 0x04, BIT(2), 0);
>> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
>> + 0x04, BIT(4), 0);
>> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
>> + 0x04, BIT(5), 0);
>> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
>> + 0x04, BIT(8), 0);
>> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
>> + 0x04, BIT(9), 0);
>> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
>> + 0x04, BIT(10), 0);
>> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
>> + 0x04, BIT(12), 0);
>> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
>> + 0x04, BIT(13), 0);
>> +
>> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
>> + 0x08, BIT(0), 0);
>> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
>> + 0x08, BIT(1), 0);
>> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
>> + 0x08, BIT(2), 0);
>> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
>> + 0x08, BIT(4), 0);
>> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
>> + 0x08, BIT(5), 0);
>> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
>> + 0x08, BIT(8), 0);
>> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
>> + 0x08, BIT(9), 0);
>> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
>> + 0x08, BIT(10), 0);
>> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
>> + 0x08, BIT(12), 0);
>> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
>> + 0x08, BIT(13), 0);
>> +
>> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
>> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
>> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
>> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
>> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
>> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
>
> I couldn't find any documentation for this CCU.
I dug this up in the released Allwinner kernel.
> What are those clocks for, and how the display engine should be using
> (ie, which one is it expecting to drive / ungate / etc.)
Allwinner basically put all DE-related clock controls into a
separate module. In here, as the names above suggest, we have
bus gates, dram gates, and module clocks for each part of the
display pipeline. As with older SoCs that have DE 1.0, each
module should ungate and use the clocks related to them.
I'll put something like the above in the commit message.
ChenYu
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
[toc] | [prev] | [next] | [standalone]
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-01-27 10:30 +0100 |
| Subject | Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU |
| Message-ID | <t4b0Z-2kf-5@gated-at.bofh.it> |
| In reply to | #1567337 |
On Fri, Jan 27, 2017 at 4:58 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote:
>> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > Hi,
>> >
>> > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote:
>> >> Add support for the display engine clock controls found on the A80.
>> >>
>> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> >> ---
>> >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++
>> >> drivers/clk/sunxi-ng/Makefile | 1 +
>> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++
>> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++
>> >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++
>> >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++
>> >> 6 files changed, 483 insertions(+)
>> >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
>> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
>> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
>> >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h
>> >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h
>> >>
>> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
>> >> new file mode 100644
>> >> index 000000000000..3a5e6df70677
>> >> --- /dev/null
>> >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
>> >> @@ -0,0 +1,28 @@
>> >> +Allwinner A80 Display Engine Clock Control Binding
>> >> +------------------------------------
>> >> +
>> >> +Required properties :
>> >> +- compatible: must contain one of the following compatibles:
>> >> + - "allwinner,sun9i-a80-de-clocks"
>> >> +
>> >> +- reg: Must contain the registers base address and length
>> >> +- clocks: phandle to the clocks feeding the display engine subsystem.
>> >> + Three are needed:
>> >> + - "mod": the display engine module clock
>> >> + - "dram": the DRAM bus clock for the system
>> >> + - "bus": the bus clock for the whole display engine subsystem
>> >> +- clock-names: Must contain the clock names described just above
>> >> +- resets: phandle to the reset control for the display engine subsystem.
>> >> +- #clock-cells : must contain 1
>> >> +- #reset-cells : must contain 1
>> >> +
>> >> +Example:
>> >> +de_clocks: clock@03000000 {
>> >> + compatible = "allwinner,sun9i-a80-de-clks";
>> >> + reg = <0x03000000 0x30>;
>> >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
>> >> + clock-names = "mod", "dram", "bus";
>> >> + resets = <&ccu RST_BUS_DE>;
>> >> + #clock-cells = <1>;
>> >> + #reset-cells = <1>;
>> >> +};
>> >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
>> >> index 8f37ef7fb67d..6feaac0c5600 100644
>> >> --- a/drivers/clk/sunxi-ng/Makefile
>> >> +++ b/drivers/clk/sunxi-ng/Makefile
>> >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
>> >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
>> >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
>> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
>> >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
>> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
>> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
>> >> new file mode 100644
>> >> index 000000000000..3fc27db0a49a
>> >> --- /dev/null
>> >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
>> >> @@ -0,0 +1,283 @@
>> >> +/*
>> >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
>> >> + *
>> >> + * This software is licensed under the terms of the GNU General Public
>> >> + * License version 2, as published by the Free Software Foundation, and
>> >> + * may be copied, distributed, and modified under those terms.
>> >> + *
>> >> + * This program is distributed in the hope that it will be useful,
>> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> >> + * GNU General Public License for more details.
>> >> + */
>> >> +
>> >> +#include <linux/clk.h>
>> >> +#include <linux/clk-provider.h>
>> >> +#include <linux/of_address.h>
>> >> +#include <linux/platform_device.h>
>> >> +#include <linux/reset.h>
>> >> +
>> >> +#include "ccu_common.h"
>> >> +#include "ccu_div.h"
>> >> +#include "ccu_gate.h"
>> >> +#include "ccu_reset.h"
>> >> +
>> >> +#include "ccu-sun9i-a80-de.h"
>> >> +
>> >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
>> >> + 0x00, BIT(0), 0);
>> >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
>> >> + 0x00, BIT(1), 0);
>> >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
>> >> + 0x00, BIT(2), 0);
>> >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
>> >> + 0x00, BIT(4), 0);
>> >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
>> >> + 0x00, BIT(5), 0);
>> >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
>> >> + 0x00, BIT(8), 0);
>> >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
>> >> + 0x00, BIT(9), 0);
>> >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
>> >> + 0x00, BIT(10), 0);
>> >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
>> >> + 0x00, BIT(12), 0);
>> >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
>> >> + 0x00, BIT(13), 0);
>> >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de",
>> >> + 0x00, BIT(20), 0);
>> >> +
>> >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
>> >> + 0x04, BIT(0), 0);
>> >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
>> >> + 0x04, BIT(1), 0);
>> >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
>> >> + 0x04, BIT(2), 0);
>> >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
>> >> + 0x04, BIT(4), 0);
>> >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
>> >> + 0x04, BIT(5), 0);
>> >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
>> >> + 0x04, BIT(8), 0);
>> >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
>> >> + 0x04, BIT(9), 0);
>> >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
>> >> + 0x04, BIT(10), 0);
>> >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
>> >> + 0x04, BIT(12), 0);
>> >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
>> >> + 0x04, BIT(13), 0);
>> >> +
>> >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
>> >> + 0x08, BIT(0), 0);
>> >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
>> >> + 0x08, BIT(1), 0);
>> >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
>> >> + 0x08, BIT(2), 0);
>> >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
>> >> + 0x08, BIT(4), 0);
>> >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
>> >> + 0x08, BIT(5), 0);
>> >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
>> >> + 0x08, BIT(8), 0);
>> >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
>> >> + 0x08, BIT(9), 0);
>> >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
>> >> + 0x08, BIT(10), 0);
>> >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
>> >> + 0x08, BIT(12), 0);
>> >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
>> >> + 0x08, BIT(13), 0);
>> >> +
>> >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
>> >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
>> >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
>> >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
>> >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
>> >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
>> >
>> > I couldn't find any documentation for this CCU.
>>
>> I dug this up in the released Allwinner kernel.
>>
>> > What are those clocks for, and how the display engine should be using
>> > (ie, which one is it expecting to drive / ungate / etc.)
>>
>> Allwinner basically put all DE-related clock controls into a
>> separate module. In here, as the names above suggest, we have
>> bus gates, dram gates, and module clocks for each part of the
>> display pipeline. As with older SoCs that have DE 1.0, each
>> module should ungate and use the clocks related to them.
>>
>> I'll put something like the above in the commit message.
>
> So the module clocks are a combination of a divider and a clock?
Correct. Some have dividers, some don't.
> And I'm guessing the reason you separated them is because they belong
> in a different register.
Correct. Trying to support them within one clock would be a big
deviation from what sunxi-ng currently supports. I left the
divider clocks at the end of the list, and aren't exported to
dt either. So if we really want to get rid of those intermediate
divider clocks, we can do so later without affecting the exposed
interface.
Regards
ChenYu
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-01-27 10:50 +0100 |
| Subject | Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU |
| Message-ID | <t4bkl-2qx-7@gated-at.bofh.it> |
| In reply to | #1567981 |
[Multipart message — attachments visible in raw view] — view raw
On Fri, Jan 27, 2017 at 05:26:53PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 27, 2017 at 4:58 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote:
> >> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard
> >> <maxime.ripard@free-electrons.com> wrote:
> >> > Hi,
> >> >
> >> > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote:
> >> >> Add support for the display engine clock controls found on the A80.
> >> >>
> >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> >> ---
> >> >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++
> >> >> drivers/clk/sunxi-ng/Makefile | 1 +
> >> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++
> >> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++
> >> >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++
> >> >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++
> >> >> 6 files changed, 483 insertions(+)
> >> >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
> >> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> >> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
> >> >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h
> >> >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h
> >> >>
> >> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
> >> >> new file mode 100644
> >> >> index 000000000000..3a5e6df70677
> >> >> --- /dev/null
> >> >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
> >> >> @@ -0,0 +1,28 @@
> >> >> +Allwinner A80 Display Engine Clock Control Binding
> >> >> +------------------------------------
> >> >> +
> >> >> +Required properties :
> >> >> +- compatible: must contain one of the following compatibles:
> >> >> + - "allwinner,sun9i-a80-de-clocks"
> >> >> +
> >> >> +- reg: Must contain the registers base address and length
> >> >> +- clocks: phandle to the clocks feeding the display engine subsystem.
> >> >> + Three are needed:
> >> >> + - "mod": the display engine module clock
> >> >> + - "dram": the DRAM bus clock for the system
> >> >> + - "bus": the bus clock for the whole display engine subsystem
> >> >> +- clock-names: Must contain the clock names described just above
> >> >> +- resets: phandle to the reset control for the display engine subsystem.
> >> >> +- #clock-cells : must contain 1
> >> >> +- #reset-cells : must contain 1
> >> >> +
> >> >> +Example:
> >> >> +de_clocks: clock@03000000 {
> >> >> + compatible = "allwinner,sun9i-a80-de-clks";
> >> >> + reg = <0x03000000 0x30>;
> >> >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
> >> >> + clock-names = "mod", "dram", "bus";
> >> >> + resets = <&ccu RST_BUS_DE>;
> >> >> + #clock-cells = <1>;
> >> >> + #reset-cells = <1>;
> >> >> +};
> >> >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> >> >> index 8f37ef7fb67d..6feaac0c5600 100644
> >> >> --- a/drivers/clk/sunxi-ng/Makefile
> >> >> +++ b/drivers/clk/sunxi-ng/Makefile
> >> >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> >> >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
> >> >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
> >> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
> >> >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
> >> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
> >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> >> >> new file mode 100644
> >> >> index 000000000000..3fc27db0a49a
> >> >> --- /dev/null
> >> >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> >> >> @@ -0,0 +1,283 @@
> >> >> +/*
> >> >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
> >> >> + *
> >> >> + * This software is licensed under the terms of the GNU General Public
> >> >> + * License version 2, as published by the Free Software Foundation, and
> >> >> + * may be copied, distributed, and modified under those terms.
> >> >> + *
> >> >> + * This program is distributed in the hope that it will be useful,
> >> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> >> + * GNU General Public License for more details.
> >> >> + */
> >> >> +
> >> >> +#include <linux/clk.h>
> >> >> +#include <linux/clk-provider.h>
> >> >> +#include <linux/of_address.h>
> >> >> +#include <linux/platform_device.h>
> >> >> +#include <linux/reset.h>
> >> >> +
> >> >> +#include "ccu_common.h"
> >> >> +#include "ccu_div.h"
> >> >> +#include "ccu_gate.h"
> >> >> +#include "ccu_reset.h"
> >> >> +
> >> >> +#include "ccu-sun9i-a80-de.h"
> >> >> +
> >> >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
> >> >> + 0x00, BIT(0), 0);
> >> >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
> >> >> + 0x00, BIT(1), 0);
> >> >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
> >> >> + 0x00, BIT(2), 0);
> >> >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
> >> >> + 0x00, BIT(4), 0);
> >> >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
> >> >> + 0x00, BIT(5), 0);
> >> >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
> >> >> + 0x00, BIT(8), 0);
> >> >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
> >> >> + 0x00, BIT(9), 0);
> >> >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
> >> >> + 0x00, BIT(10), 0);
> >> >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
> >> >> + 0x00, BIT(12), 0);
> >> >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
> >> >> + 0x00, BIT(13), 0);
> >> >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de",
> >> >> + 0x00, BIT(20), 0);
> >> >> +
> >> >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
> >> >> + 0x04, BIT(0), 0);
> >> >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
> >> >> + 0x04, BIT(1), 0);
> >> >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
> >> >> + 0x04, BIT(2), 0);
> >> >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
> >> >> + 0x04, BIT(4), 0);
> >> >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
> >> >> + 0x04, BIT(5), 0);
> >> >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
> >> >> + 0x04, BIT(8), 0);
> >> >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
> >> >> + 0x04, BIT(9), 0);
> >> >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
> >> >> + 0x04, BIT(10), 0);
> >> >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
> >> >> + 0x04, BIT(12), 0);
> >> >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
> >> >> + 0x04, BIT(13), 0);
> >> >> +
> >> >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
> >> >> + 0x08, BIT(0), 0);
> >> >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
> >> >> + 0x08, BIT(1), 0);
> >> >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
> >> >> + 0x08, BIT(2), 0);
> >> >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
> >> >> + 0x08, BIT(4), 0);
> >> >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
> >> >> + 0x08, BIT(5), 0);
> >> >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
> >> >> + 0x08, BIT(8), 0);
> >> >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
> >> >> + 0x08, BIT(9), 0);
> >> >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
> >> >> + 0x08, BIT(10), 0);
> >> >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
> >> >> + 0x08, BIT(12), 0);
> >> >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
> >> >> + 0x08, BIT(13), 0);
> >> >> +
> >> >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
> >> >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
> >> >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
> >> >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
> >> >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
> >> >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
> >> >
> >> > I couldn't find any documentation for this CCU.
> >>
> >> I dug this up in the released Allwinner kernel.
> >>
> >> > What are those clocks for, and how the display engine should be using
> >> > (ie, which one is it expecting to drive / ungate / etc.)
> >>
> >> Allwinner basically put all DE-related clock controls into a
> >> separate module. In here, as the names above suggest, we have
> >> bus gates, dram gates, and module clocks for each part of the
> >> display pipeline. As with older SoCs that have DE 1.0, each
> >> module should ungate and use the clocks related to them.
> >>
> >> I'll put something like the above in the commit message.
> >
> > So the module clocks are a combination of a divider and a clock?
>
> Correct. Some have dividers, some don't.
>
> > And I'm guessing the reason you separated them is because they belong
> > in a different register.
>
> Correct. Trying to support them within one clock would be a big
> deviation from what sunxi-ng currently supports. I left the
> divider clocks at the end of the list, and aren't exported to
> dt either. So if we really want to get rid of those intermediate
> divider clocks, we can do so later without affecting the exposed
> interface.
That works for me, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-01-27 21:10 +0100 |
| Subject | Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU |
| Message-ID | <t4b0Z-2kf-7@gated-at.bofh.it> |
| In reply to | #1567337 |
[Multipart message — attachments visible in raw view] — view raw
On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote:
> >> Add support for the display engine clock controls found on the A80.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++
> >> drivers/clk/sunxi-ng/Makefile | 1 +
> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++
> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++
> >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++
> >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++
> >> 6 files changed, 483 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
> >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h
> >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt
> >> new file mode 100644
> >> index 000000000000..3a5e6df70677
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt
> >> @@ -0,0 +1,28 @@
> >> +Allwinner A80 Display Engine Clock Control Binding
> >> +------------------------------------
> >> +
> >> +Required properties :
> >> +- compatible: must contain one of the following compatibles:
> >> + - "allwinner,sun9i-a80-de-clocks"
> >> +
> >> +- reg: Must contain the registers base address and length
> >> +- clocks: phandle to the clocks feeding the display engine subsystem.
> >> + Three are needed:
> >> + - "mod": the display engine module clock
> >> + - "dram": the DRAM bus clock for the system
> >> + - "bus": the bus clock for the whole display engine subsystem
> >> +- clock-names: Must contain the clock names described just above
> >> +- resets: phandle to the reset control for the display engine subsystem.
> >> +- #clock-cells : must contain 1
> >> +- #reset-cells : must contain 1
> >> +
> >> +Example:
> >> +de_clocks: clock@03000000 {
> >> + compatible = "allwinner,sun9i-a80-de-clks";
> >> + reg = <0x03000000 0x30>;
> >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
> >> + clock-names = "mod", "dram", "bus";
> >> + resets = <&ccu RST_BUS_DE>;
> >> + #clock-cells = <1>;
> >> + #reset-cells = <1>;
> >> +};
> >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> >> index 8f37ef7fb67d..6feaac0c5600 100644
> >> --- a/drivers/clk/sunxi-ng/Makefile
> >> +++ b/drivers/clk/sunxi-ng/Makefile
> >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
> >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
> >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
> >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> >> new file mode 100644
> >> index 000000000000..3fc27db0a49a
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
> >> @@ -0,0 +1,283 @@
> >> +/*
> >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
> >> + *
> >> + * This software is licensed under the terms of the GNU General Public
> >> + * License version 2, as published by the Free Software Foundation, and
> >> + * may be copied, distributed, and modified under those terms.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> + */
> >> +
> >> +#include <linux/clk.h>
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/of_address.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/reset.h>
> >> +
> >> +#include "ccu_common.h"
> >> +#include "ccu_div.h"
> >> +#include "ccu_gate.h"
> >> +#include "ccu_reset.h"
> >> +
> >> +#include "ccu-sun9i-a80-de.h"
> >> +
> >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
> >> + 0x00, BIT(0), 0);
> >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
> >> + 0x00, BIT(1), 0);
> >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
> >> + 0x00, BIT(2), 0);
> >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
> >> + 0x00, BIT(4), 0);
> >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
> >> + 0x00, BIT(5), 0);
> >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
> >> + 0x00, BIT(8), 0);
> >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div",
> >> + 0x00, BIT(9), 0);
> >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div",
> >> + 0x00, BIT(10), 0);
> >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de",
> >> + 0x00, BIT(12), 0);
> >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de",
> >> + 0x00, BIT(13), 0);
> >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de",
> >> + 0x00, BIT(20), 0);
> >> +
> >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
> >> + 0x04, BIT(0), 0);
> >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
> >> + 0x04, BIT(1), 0);
> >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
> >> + 0x04, BIT(2), 0);
> >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
> >> + 0x04, BIT(4), 0);
> >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
> >> + 0x04, BIT(5), 0);
> >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
> >> + 0x04, BIT(8), 0);
> >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
> >> + 0x04, BIT(9), 0);
> >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
> >> + 0x04, BIT(10), 0);
> >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
> >> + 0x04, BIT(12), 0);
> >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
> >> + 0x04, BIT(13), 0);
> >> +
> >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de",
> >> + 0x08, BIT(0), 0);
> >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de",
> >> + 0x08, BIT(1), 0);
> >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de",
> >> + 0x08, BIT(2), 0);
> >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de",
> >> + 0x08, BIT(4), 0);
> >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de",
> >> + 0x08, BIT(5), 0);
> >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de",
> >> + 0x08, BIT(8), 0);
> >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de",
> >> + 0x08, BIT(9), 0);
> >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de",
> >> + 0x08, BIT(10), 0);
> >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de",
> >> + 0x08, BIT(12), 0);
> >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de",
> >> + 0x08, BIT(13), 0);
> >> +
> >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0);
> >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0);
> >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0);
> >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0);
> >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0);
> >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0);
> >
> > I couldn't find any documentation for this CCU.
>
> I dug this up in the released Allwinner kernel.
>
> > What are those clocks for, and how the display engine should be using
> > (ie, which one is it expecting to drive / ungate / etc.)
>
> Allwinner basically put all DE-related clock controls into a
> separate module. In here, as the names above suggest, we have
> bus gates, dram gates, and module clocks for each part of the
> display pipeline. As with older SoCs that have DE 1.0, each
> module should ungate and use the clocks related to them.
>
> I'll put something like the above in the commit message.
So the module clocks are a combination of a divider and a clock?
And I'm guessing the reason you separated them is because they belong
in a different register.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Priit Laes <plaes@plaes.org> |
|---|---|
| Date | 2017-01-24 07:20 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs |
| Message-ID | <t32Cu-Fq-9@gated-at.bofh.it> |
| In reply to | #1565442 |
On Tue, 2017-01-24 at 10:32 +0800, Chen-Yu Tsai wrote: > Hi everyone, Hi! Thanks for working on that! You might want to bump the copyright year starting from patch 5. [...] Päikest, Priit Laes
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2017-01-27 22:20 +0100 |
| Subject | Re: [PATCH 05/11] clk: sunxi-ng: Add A80 CCU |
| Message-ID | <t4m66-Rh-5@gated-at.bofh.it> |
| In reply to | #1565442 |
On Tue, Jan 24, 2017 at 10:32:24AM +0800, Chen-Yu Tsai wrote: > Add support for the main clock unit found in the A80. > > Note that on the A80, some subsystems have separate clock controllers > downstream of the main clock unit. These include the MMC, USB, and > display engine subsystems. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + Acked-by: Rob Herring <robh@kernel.org> > drivers/clk/sunxi-ng/Kconfig | 10 + > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 1223 ++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun9i-a80.h | 57 + > include/dt-bindings/clock/sun9i-a80-ccu.h | 162 +++ > include/dt-bindings/reset/sun9i-a80-ccu.h | 102 ++ > 7 files changed, 1556 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.h > create mode 100644 include/dt-bindings/clock/sun9i-a80-ccu.h > create mode 100644 include/dt-bindings/reset/sun9i-a80-ccu.h
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