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[PATCH] clk: meson8b: fix clk81 register address

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  [PATCH] clk: meson8b: fix clk81 register address Jerome Brunet <jbrunet@baylibre.com> - 2017-01-25 12:00 +0100
    Re: [PATCH] clk: meson8b: fix clk81 register address Jerome Brunet <jbrunet@baylibre.com> - 2017-01-26 15:30 +0100
    Re: [PATCH] clk: meson8b: fix clk81 register address Stephen Boyd <sboyd@codeaurora.org> - 2017-01-27 01:00 +0100
      Re: [PATCH] clk: meson8b: fix clk81 register address Jerome Brunet <jbrunet@baylibre.com> - 2017-01-27 09:50 +0100

#1566481 — [PATCH] clk: meson8b: fix clk81 register address

During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.

As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.

Fixed by just removing the second fixup.

Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 Patch based on khilman/linux-amlogic.git master branch.

 I don't have a meson8b HW so this patch so this patch has not been
 tested on real HW.

 drivers/clk/meson/meson8b.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 3f1be46cbb33..888494d4fb8a 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -607,7 +607,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
 	/* Populate the base address for the MPEG clks */
 	meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
 	meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
-	meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
 
 	/* Populate base address for gates */
 	for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
-- 
2.7.4

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#1567460

On Wed, 2017-01-25 at 11:53 +0100, Jerome Brunet wrote:
> During meson8b clock probe, clk81 register address is fixed twice.
> First using the meson8b_clk_gates array, then by directly changing
> meson8b_clk81 register.
> 
> As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base +
> clk_base.
> 
> Fixed by just removing the second fixup.
> 
> Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  Patch based on khilman/linux-amlogic.git master branch.
> 
>  I don't have a meson8b HW so this patch so this patch has not been
>  tested on real HW.

I got my hands on an odroidc1 and I have been to test this.
With clk_base @ 0xf0965000:

* without the patch:
clk81.reg = 0xe12ca174

* with the patch:
clk81.reg = 0xf0965174 (expected result)

In the past, we probably did not see this because clk81 is the mother
of all the other clock gate around the SoC so it is very likely that u-
boot opened this gate for us.

> 
>  drivers/clk/meson/meson8b.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.c
> b/drivers/clk/meson/meson8b.c
> index 3f1be46cbb33..888494d4fb8a 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -607,7 +607,6 @@ static int meson8b_clkc_probe(struct
> platform_device *pdev)
>  	/* Populate the base address for the MPEG clks */
>  	meson8b_mpeg_clk_sel.reg = clk_base +
> (u32)meson8b_mpeg_clk_sel.reg;
>  	meson8b_mpeg_clk_div.reg = clk_base +
> (u32)meson8b_mpeg_clk_div.reg;
> -	meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
>  
>  	/* Populate base address for gates */
>  	for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)

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#1567824

On 01/25, Jerome Brunet wrote:
> During meson8b clock probe, clk81 register address is fixed twice.
> First using the meson8b_clk_gates array, then by directly changing
> meson8b_clk81 register.
> 
> As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.
> 
> Fixed by just removing the second fixup.
> 
> Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
>  Patch based on khilman/linux-amlogic.git master branch.

The problem isn't introduced there though?

> 
>  I don't have a meson8b HW so this patch so this patch has not been
>  tested on real HW.

Applied to clk-next.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1567953

On Thu, 2017-01-26 at 15:57 -0800, Stephen Boyd wrote:
> On 01/25, Jerome Brunet wrote:
> > 
> > During meson8b clock probe, clk81 register address is fixed twice.
> > First using the meson8b_clk_gates array, then by directly changing
> > meson8b_clk81 register.
> > 
> > As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base +
> > clk_base.
> > 
> > Fixed by just removing the second fixup.
> > 
> > Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > ---
> >  Patch based on khilman/linux-amlogic.git master branch.
> 
> The problem isn't introduced there though?
Indeed, I should have based my patch on clk-next. Will do next time.

> 
> > 
> > 
> >  I don't have a meson8b HW so this patch so this patch has not been
> >  tested on real HW.
> 
> Applied to clk-next.
> 

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