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[PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register

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  [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register Chen-Yu Tsai <wens@csie.org> - 2017-01-24 03:40 +0100
    Re: [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock  status register Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-01-26 11:00 +0100

#1565436 — [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register

On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.

Add a flag to support this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi-ng/ccu_common.c | 8 ++++++--
 drivers/clk/sunxi-ng/ccu_common.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 51d4bac97ab3..3fd0c3331aff 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -25,13 +25,17 @@ static DEFINE_SPINLOCK(ccu_lock);
 
 void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
 {
+	void __iomem *addr;
 	u32 reg;
 
 	if (!lock)
 		return;
 
-	WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
-					   reg & lock, 100, 70000));
+	addr = common->base + common->reg;
+	if (common->features & CCU_FEATURE_LOCK_REG)
+		addr = common->base + common->lock_reg;
+
+	WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
 }
 
 int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index cdd69eb2e0b9..73d81dc58fc5 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -22,6 +22,7 @@
 #define CCU_FEATURE_FIXED_PREDIV	BIT(2)
 #define CCU_FEATURE_FIXED_POSTDIV	BIT(3)
 #define CCU_FEATURE_ALL_PREDIV		BIT(4)
+#define CCU_FEATURE_LOCK_REG		BIT(5)
 
 struct device_node;
 
@@ -57,6 +58,7 @@ struct device_node;
 struct ccu_common {
 	void __iomem	*base;
 	u16		reg;
+	u16		lock_reg;
 	u32		prediv;
 
 	unsigned long	features;
-- 
2.11.0

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#1567251 — Re: [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Tue, Jan 24, 2017 at 10:32:23AM +0800, Chen-Yu Tsai wrote:
> On the Allwinner A80 SoC, the PLL lock status indicators are grouped
> together in a separate register, as opposed to being scattered in each
> PLL's configuration register.
> 
> Add a flag to support this.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/clk/sunxi-ng/ccu_common.c | 8 ++++++--
>  drivers/clk/sunxi-ng/ccu_common.h | 2 ++
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
> index 51d4bac97ab3..3fd0c3331aff 100644
> --- a/drivers/clk/sunxi-ng/ccu_common.c
> +++ b/drivers/clk/sunxi-ng/ccu_common.c
> @@ -25,13 +25,17 @@ static DEFINE_SPINLOCK(ccu_lock);
>  
>  void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
>  {
> +	void __iomem *addr;
>  	u32 reg;
>  
>  	if (!lock)
>  		return;
>  
> -	WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
> -					   reg & lock, 100, 70000));
> +	addr = common->base + common->reg;
> +	if (common->features & CCU_FEATURE_LOCK_REG)
> +		addr = common->base + common->lock_reg;

I'd rather have an else here (but it's really just a nitpick).

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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