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[v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention

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  [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
      Re: [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions "H. Peter Anvin" <hpa@zytor.com> - 2017-01-25 21:50 +0100
        Re: [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:00 +0100
    [v3 PATCH 01/10] x86/mpx: Do not use SIB index if index points to R/ESP Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    [v3 PATCH 09/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    [v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
      Re: [v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util  functions to a new insn-kernel Masami Hiramatsu <mhiramat@kernel.org> - 2017-01-26 03:30 +0100
    [v3 PATCH 10/10] selftests/x86: Add tests for User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
      Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Andy Lutomirski <luto@amacapital.net> - 2017-01-25 23:00 +0100
        Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings "H. Peter Anvin" <hpa@zytor.com> - 2017-01-25 23:10 +0100
        Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:00 +0100
          Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Andy Lutomirski <luto@amacapital.net> - 2017-01-26 18:20 +0100
            Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-27 04:50 +0100
    [v3 PATCH 02/10] x86/mpx: Fail decoding when SIB baseR/EBP is and no displacement is used Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    [v3 PATCH 08/10] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
      Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain  register offset in ModRM Masami Hiramatsu <mhiramat@kernel.org> - 2017-01-26 03:20 +0100
        Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain  register offset in ModRM Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:10 +0100
          Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain  register offset in ModRM Masami Hiramatsu <mhiramat@kernel.org> - 2017-01-27 09:00 +0100
    Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention "H. Peter Anvin" <hpa@zytor.com> - 2017-01-25 21:50 +0100
      Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:00 +0100

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#1567924 — Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM

On Wed, 25 Jan 2017 22:07:16 -0800
Ricardo Neri <ricardo.neri-calderon@linux.intel.com> wrote:

> Hi Masami,
> 
> On Thu, 2017-01-26 at 11:11 +0900, Masami Hiramatsu wrote:
> > On Wed, 25 Jan 2017 12:23:47 -0800
> > Ricardo Neri <ricardo.neri-calderon@linux.intel.com> wrote:
> > 
> > > The function insn_get_reg_offset requires a type to indicate whether
> > > the returned offset is that given by by the ModRM or the SIB byte.
> > > Callers of this function would need the definition of the type struct.
> > > This is not needed. Instead, auxiliary functions can be defined for
> > > this purpose.
> > > 
> > > When the operand is a register, the emulation code for User-Mode
> > > Instruction Prevention needs to know the offset of the register indicated
> > > in the r/m part of the ModRM byte. Thus, start by adding an auxiliary
> > > function for this purpose.
> > 
> > Hmm, why wouldn't you just rename it to insn_get_reg_offset() and export it?
> 
> Do you mean exporting the structure that I mention above? The problem
> that I am trying to solve is that callers sometimes want to know the
> offset of the register encoded in the SiB or the ModRM bytes. I could
> use something 
> 
> insn_get_reg_offset(insn, regs, INSN_TYPE_MODRM)
> insn_get_reg_offset(insn, regs, INSN_TYPE_SIB)
> 
> Instead, I opted for
> 
> insn_get_reg_offset_rm(insn, regs)
> insn_get_reg_offset_sib(insn, regs)
> 
> to avoid exposing an enum with the INSN_TYPE_MODRM, INSN_TYPE_SIB.

OK, if so, I think you should export both of them at once, not only
insn_get_reg_offset_rm().

Thank you,

> 
> If you feel that the former makes more sense, I can change the
> implementation.
> 
> Thanks and BR,
> Ricardo
> > 
> > Thank you,
> > 
> > > 
> > > Cc: Dave Hansen <dave.hansen@linux.intel.com>
> > > Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
> > > Cc: Colin Ian King <colin.king@canonical.com>
> > > Cc: Lorenzo Stoakes <lstoakes@gmail.com>
> > > Cc: Qiaowei Ren <qiaowei.ren@intel.com>
> > > Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
> > > Cc: Masami Hiramatsu <mhiramat@kernel.org>
> > > Cc: Adrian Hunter <adrian.hunter@intel.com>
> > > Cc: Kees Cook <keescook@chromium.org>
> > > Cc: Thomas Garnier <thgarnie@google.com>
> > > Cc: Peter Zijlstra <peterz@infradead.org>
> > > Cc: Borislav Petkov <bp@suse.de>
> > > Cc: Dmitry Vyukov <dvyukov@google.com>
> > > Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
> > > Cc: x86@kernel.org
> > > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
> > > ---
> > >  arch/x86/include/asm/insn-kernel.h | 1 +
> > >  arch/x86/lib/insn-kernel.c         | 5 +++++
> > >  2 files changed, 6 insertions(+)
> > > 
> > > diff --git a/arch/x86/include/asm/insn-kernel.h b/arch/x86/include/asm/insn-kernel.h
> > > index aef416a..3f34649 100644
> > > --- a/arch/x86/include/asm/insn-kernel.h
> > > +++ b/arch/x86/include/asm/insn-kernel.h
> > > @@ -12,5 +12,6 @@
> > >  #include <asm/ptrace.h>
> > >  
> > >  void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs);
> > > +int insn_get_reg_offset_rm(struct insn *insn, struct pt_regs *regs);
> > >  
> > >  #endif /* _ASM_X86_INSN_KERNEL_H */
> > > diff --git a/arch/x86/lib/insn-kernel.c b/arch/x86/lib/insn-kernel.c
> > > index 8072abe..267cab4 100644
> > > --- a/arch/x86/lib/insn-kernel.c
> > > +++ b/arch/x86/lib/insn-kernel.c
> > > @@ -95,6 +95,11 @@ static int get_reg_offset(struct insn *insn, struct pt_regs *regs,
> > >  	return regoff[regno];
> > >  }
> > >  
> > > +int insn_get_reg_offset_rm(struct insn *insn, struct pt_regs *regs)
> > > +{
> > > +	return get_reg_offset(insn, regs, REG_TYPE_RM);
> > > +}
> > > +
> > >  /*
> > >   * return the address being referenced be instruction
> > >   * for rm=3 returning the content of the rm reg
> > > -- 
> > > 2.9.3
> > > 
> > 
> > 
> 
> 


-- 
Masami Hiramatsu <mhiramat@kernel.org>

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#1566941

On 01/25/17 12:23, Ricardo Neri wrote:
>  * SMSW returns the value with which the CR0 register is programmed in
>    head_32/64.S at boot time. This is, the following bits are enabed:
>    CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
>    Extension Type, which will always be 1 in recent processors with UMIP;
>    CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment
>    Mask. Additionally, in x86_64, CR0.31 for Paging is set.

SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd.

	-hpa

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#1567122

Hi Peter,
On Wed, 2017-01-25 at 12:34 -0800, H. Peter Anvin wrote:
> On 01/25/17 12:23, Ricardo Neri wrote:
> >  * SMSW returns the value with which the CR0 register is programmed in
> >    head_32/64.S at boot time. This is, the following bits are enabed:
> >    CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
> >    Extension Type, which will always be 1 in recent processors with UMIP;
> >    CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment
> >    Mask. Additionally, in x86_64, CR0.31 for Paging is set.
> 
> SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd.

I checked again the latest version (from Dec 2016) of the Intel Software
Development Manual. The documentation for SMSW states the following:

SMSW r16 operand size 16, store CR0[15:0] in r16
SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64

When the operand is a memory location, yes, it only returns CR0[15:0]

Also, in the tests that I ran I wrote the result of SMSW to a 64-bit
register. I get 0x80050033. It seems to me that it does write as many
bits as the register operand can hold.

Am I missing something?

Thanks and BR,
Ricardo
> 
> 	-hpa
> 
> 

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