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| Started by | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| First post | 2017-01-23 06:30 +0100 |
| Last post | 2017-01-23 06:30 +0100 |
| Articles | 1 — 1 participant |
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[PATCH] aspeed: dts: g5: Update GPIO pin range to mux extra banks Andrew Jeffery <andrew@aj.id.au> - 2017-01-23 06:30 +0100
| From | Andrew Jeffery <andrew@aj.id.au> |
|---|---|
| Date | 2017-01-23 06:30 +0100 |
| Subject | [PATCH] aspeed: dts: g5: Update GPIO pin range to mux extra banks |
| Message-ID | <t2Fmy-2m8-13@gated-at.bofh.it> |
The Aspeed GPIO driver recently gained support for banks Y, Z, AA, AB and AC.
Update the devicetree so GPIO requests for these pins are routed via pinmux,
else the export succeeds but the GPIOs are non-functional.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index b664fe380936..a9305b964b11 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -920,8 +920,8 @@
compatible = "aspeed,ast2500-gpio";
reg = <0x1e780000 0x1000>;
interrupts = <20>;
- gpio-ranges = <&pinctrl 0 0 220>;
interrupt-controller;
+ gpio-ranges = <&pinctrl 0 0 232>;
};
timer: timer@1e782000 {
--
2.9.3
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