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[PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect

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  [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect Vikas Shivappa <vikas.shivappa@linux.intel.com> - 2017-01-10 20:40 +0100
    Re: [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature  detect Thomas Gleixner <tglx@linutronix.de> - 2017-01-16 15:00 +0100
      Re: [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature  detect Peter Zijlstra <peterz@infradead.org> - 2017-01-16 15:50 +0100
        Re: [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature  detect Thomas Gleixner <tglx@linutronix.de> - 2017-01-16 17:20 +0100

#1555851 — [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect

Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
Add supporting data structures to detect feature details which is done
in later patch using CPUID with EAX=10H, ECX= 3.

Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
---
 arch/x86/include/asm/cpufeatures.h |  2 ++
 arch/x86/include/asm/intel_rdt.h   | 10 +++++++++-
 arch/x86/kernel/cpu/intel_rdt.c    |  4 ++++
 arch/x86/kernel/cpu/scattered.c    |  1 +
 4 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee31..50cbdd0 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -201,6 +201,8 @@
 #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
 #define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation Single precision */
 
+#define X86_FEATURE_MBA         ( 7*32+18) /* Memory Bandwidth Allocation */
+
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */
 #define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index e1f8acb..35e76b4 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -180,7 +180,15 @@ enum {
 	unsigned int full;
 };
 
-/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
+/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
+union cpuid_0x10_3_eax {
+	struct {
+		unsigned int max_delay:12;
+	} split;
+	unsigned int full;
+};
+
+/* CPUID.(EAX=10H, ECX=ResID).EDX */
 union cpuid_0x10_x_edx {
 	struct {
 		unsigned int cos_max:16;
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index b2c037a..fced83c 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -184,6 +184,10 @@ static inline bool get_rdt_resources(void)
 		ret = true;
 	}
 
+	if (boot_cpu_has(X86_FEATURE_MBA)) {
+		ret = true;
+	}
+
 	return ret;
 }
 
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index d979406..23c2350 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -27,6 +27,7 @@ struct cpuid_bit {
 	{ X86_FEATURE_CAT_L3,		CPUID_EBX,  1, 0x00000010, 0 },
 	{ X86_FEATURE_CAT_L2,		CPUID_EBX,  2, 0x00000010, 0 },
 	{ X86_FEATURE_CDP_L3,		CPUID_ECX,  2, 0x00000010, 1 },
+	{ X86_FEATURE_MBA,		CPUID_EBX,  3, 0x00000010, 0 },
 	{ X86_FEATURE_HW_PSTATE,	CPUID_EDX,  7, 0x80000007, 0 },
 	{ X86_FEATURE_CPB,		CPUID_EDX,  9, 0x80000007, 0 },
 	{ X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },
-- 
1.9.1

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#1559762 — Re: [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect

On Tue, 10 Jan 2017, Vikas Shivappa wrote:

> Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
> Add supporting data structures to detect feature details which is done
> in later patch using CPUID with EAX=10H, ECX= 3.

So why is the $subject of this patch claiming that it provides the feature
detection?

> -/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
> +/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
> +union cpuid_0x10_3_eax {
> +	struct {
> +		unsigned int max_delay:12;
> +	} split;

And the point of this struct is?

> +	unsigned int full;
> +};

> +	if (boot_cpu_has(X86_FEATURE_MBA)) {
> +		ret = true;
> +	}

Pointless brackets.

Thanks,

	tglx

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#1559796 — Re: [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect

On Mon, Jan 16, 2017 at 02:59:11PM +0100, Thomas Gleixner wrote:
> On Tue, 10 Jan 2017, Vikas Shivappa wrote:
> 
> > Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
> > Add supporting data structures to detect feature details which is done
> > in later patch using CPUID with EAX=10H, ECX= 3.
> 
> So why is the $subject of this patch claiming that it provides the feature
> detection?
> 
> > -/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
> > +/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
> > +union cpuid_0x10_3_eax {
> > +	struct {
> > +		unsigned int max_delay:12;
> > +	} split;
> 
> And the point of this struct is?

I suppose its there so we cannot forget adding it when we add more
bitfields in that word and to keep naming (full vs split) consistent wrt
other cpuid unions that do have multiple fields.

> 
> > +	unsigned int full;
> > +};

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#1559872 — Re: [PATCH 4/8] x86/intel_rdt/mba: Memory b/w allocation feature detect

On Mon, 16 Jan 2017, Peter Zijlstra wrote:

> On Mon, Jan 16, 2017 at 02:59:11PM +0100, Thomas Gleixner wrote:
> > On Tue, 10 Jan 2017, Vikas Shivappa wrote:
> > 
> > > Detect MBA feature if CPUID.(EAX=10H, ECX=0):EBX.L2[bit 3] = 1.
> > > Add supporting data structures to detect feature details which is done
> > > in later patch using CPUID with EAX=10H, ECX= 3.
> > 
> > So why is the $subject of this patch claiming that it provides the feature
> > detection?
> > 
> > > -/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
> > > +/* CPUID.(EAX=10H, ECX=ResID=3).EAX */
> > > +union cpuid_0x10_3_eax {
> > > +	struct {
> > > +		unsigned int max_delay:12;
> > > +	} split;
> > 
> > And the point of this struct is?
> 
> I suppose its there so we cannot forget adding it when we add more
> bitfields in that word and to keep naming (full vs split) consistent wrt
> other cpuid unions that do have multiple fields.

Fair enough.

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