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| Started by | Milo Kim <woogyom.kim@gmail.com> |
|---|---|
| First post | 2016-10-28 09:00 +0200 |
| Last post | 2016-10-31 07:10 +0100 |
| Articles | 3 — 2 participants |
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[PATCH v2 0/4] Support H3 SPI controller Milo Kim <woogyom.kim@gmail.com> - 2016-10-28 09:00 +0200
[PATCH v2 3/4] spi: sun6i: Add binding for Allwinner H3 SPI controller Milo Kim <woogyom.kim@gmail.com> - 2016-10-28 09:00 +0200
Re: [PATCH v2 3/4] spi: sun6i: Add binding for Allwinner H3 SPI controller Rob Herring <robh@kernel.org> - 2016-10-31 07:10 +0100
| From | Milo Kim <woogyom.kim@gmail.com> |
|---|---|
| Date | 2016-10-28 09:00 +0200 |
| Subject | [PATCH v2 0/4] Support H3 SPI controller |
| Message-ID | <sx9iW-4NF-9@gated-at.bofh.it> |
Allwinner H3 SPI controller has same architecture as A31.
So most configuration is identical except one thing - FIFO capacity.
A31 H3
------------------------------------
Number of controllers 4 2
Number of FIFO depth 128 64
Transfer bits 8 8
Register maps are sharable, so sun6i SPI driver is reusable with
device configuration.
Tested on Nano Pi M1 and SPI slave device is TI LP8860.
v2:
Include DTS patches
Use of_device_get_match_data() helper to get device specific data
Fix build warning of 64bit CPU architecture
(warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast])
Milo Kim (4):
ARM: dts: sun8i: Add SPI pinctrl node in H3
ARM: dts: sun8i: Add SPI controller node in H3
spi: sun6i: Add binding for Allwinner H3 SPI controller
spi: sun6i: Support Allwinner H3 SPI controller
.../devicetree/bindings/spi/spi-sun6i.txt | 25 +++++++++++-
arch/arm/boot/dts/sun8i-h3.dtsi | 46 ++++++++++++++++++++++
drivers/spi/spi-sun6i.c | 18 ++++++---
3 files changed, 82 insertions(+), 7 deletions(-)
--
2.9.3
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| From | Milo Kim <woogyom.kim@gmail.com> |
|---|---|
| Date | 2016-10-28 09:00 +0200 |
| Subject | [PATCH v2 3/4] spi: sun6i: Add binding for Allwinner H3 SPI controller |
| Message-ID | <sx9iW-4NF-35@gated-at.bofh.it> |
| In reply to | #1510881 |
H3 SPI has same architecture as A31 except FIFO capacity.
To configure the buffer size separately, compatible property should be
different. Optional DMA specifiers and example are added.
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
.../devicetree/bindings/spi/spi-sun6i.txt | 25 ++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
index 21de73d..2ec99b8 100644
--- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -1,7 +1,7 @@
-Allwinner A31 SPI controller
+Allwinner A31/H3 SPI controller
Required properties:
-- compatible: Should be "allwinner,sun6i-a31-spi".
+- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: phandle to the clocks feeding the SPI controller. Two are
@@ -12,6 +12,11 @@ Required properties:
- resets: phandle to the reset controller asserting this device in
reset
+Optional properties:
+- dmas: DMA specifiers for rx and tx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request names should include "rx" and "tx" if present.
+
Example:
spi1: spi@01c69000 {
@@ -22,3 +27,19 @@ spi1: spi@01c69000 {
clock-names = "ahb", "mod";
resets = <&ahb1_rst 21>;
};
+
+spi0: spi@01c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
--
2.9.3
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2016-10-31 07:10 +0100 |
| Subject | Re: [PATCH v2 3/4] spi: sun6i: Add binding for Allwinner H3 SPI controller |
| Message-ID | <sydXc-6Z3-25@gated-at.bofh.it> |
| In reply to | #1510884 |
On Fri, Oct 28, 2016 at 03:54:11PM +0900, Milo Kim wrote: > H3 SPI has same architecture as A31 except FIFO capacity. > To configure the buffer size separately, compatible property should be > different. Optional DMA specifiers and example are added. > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > Cc: Mark Brown <broonie@kernel.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Chen-Yu Tsai <wens@csie.org> > Signed-off-by: Milo Kim <woogyom.kim@gmail.com> > --- > .../devicetree/bindings/spi/spi-sun6i.txt | 25 ++++++++++++++++++++-- > 1 file changed, 23 insertions(+), 2 deletions(-) Acked-by: Rob Herring <robh@kernel.org>
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